As the cost per gate of FPGAs continues to plummet, developers of embedded software applications are being presented with increased opportunities to create high performance, hardware-accelerated systems. These systems—which represent applications in domains ranging from image processing and DSP to larger-scale applications for scientific computing—benefit from the massive levels of parallelism that are available when FPGAs are used as alternatives to traditional processor architectures.

This article describes how the convergence of easier-to-use, more powerful FPGA-based computing platforms and software-to-hardware design tools can make the design of accelerated FPGA-based algorithms easier and more practical … Read More → "Accelerating C Software Applications Using a CompactFlash FPGA Accelerator Card"

When I bought my first 10MB hard-disk drive, the salesman came to visit and even took me out to lunch. I was a freshman in engineering school and I was buying the $10,000 unit for my employer, a hotel chain, to use for storing reservation data. At the time, a purchase of that amount of mass storage was a major transaction, both for our little company and for our supplier. The disk drive, about the size of a modern desktop computer, was delivered and installed by a trained technician who spent an hour with us going over the operating procedures … Read More → "Shrink-wrapping EDA"

The preparation starts weeks in advance. Whole grains are stone-ground – the resulting flour combined with honey extracted from backyard beehives over a period of months. The dough is then pressed and baked on hand-forged pans in wood-fired ovens until a fine golden crust appears that can be crushed into flakes of exactly the right consistency. After cooling, the flakes are poured into handmade pottery bowls, fired the previous week after being slung from native clay dug from the local riverbed. Finally, right before breakfast, milk from cows raised on grain grown in your own field is poured over the … Read More → "Core Sample"

In most markets, there exist a set of de-facto rules. Sport-utility vehicles have bad fuel economy. Economy cars have limited cargo space. FPGAs use too much power. ASICs have staggering non-recurring engineering (NRE) costs. Generally, the players play by those rules, and the consumer enters every buying decision with a pre-defined understanding of the tradeoffs those rules imply and which basic option favors their situation. The final choice is then decided by a comparison of the less-critical factors that differentiate the products in each area. Once a design team has decided to go with a zero-NRE solution, for example, … Read More → "Redefining Structured ASIC"

In light of its critical nature, signal integrity needs to be a key criterion during the planning and design phases of high-speed systems. Ignoring signal integrity can lead to poor reliability, degraded performance, field failures and delayed product releases—all of which can trigger lost opportunities and revenues.

Today’s high-end FPGAs support a variety of single-ended and differential I/O standards, with options to control drive-strength, slew-rate and on-chip termination. If not used correctly, this flexibility offered by FPGAs can make it difficult to manage signal integrity. Selecting the right FPGA that … Read More → "Selecting the FPGA that Meets Your Signal Integrity Requirements"

You’re cruising home from work one day, and your cell phone rings. You answer (hands free of course…). It’s your boss. New plan. He’s saying something about routing, but you can’t quite make it out. Your head is spinning. Why didn’t you pay the extra thousand bucks for that GPS system? Your boss is still talking, and you’re trying to make sense of what he’s saying, but it’s all rushing together, plus you’ve reached that “Can you hear me now” section of your commute. You catch a word … Read More → "Pedal to the Metals"

Portland, OR – May 10, 2005 – FPGA Journal announced today the immediate availability of the world’s best FPGA-related article. Developed with FPGA Journal’s newest editorial technology, it’s up to 53% more interesting than our previous generation pieces. It contains absolutely the most grandiose superlatives with fewer futile forays into lackluster alliteration, providing a fountain of profound metaphoric insight into marketing trends in the programmable logic industry. Readers of this article may be up to 28% more intelligent than those perusing competitive publications such as Electronic Engineering Times. (If you’re bringing the average down, please stop reading … Read More → "World’s Best FPGA Article"

Today there are 1.6 billion wireless subscribers in the world with the number anticipated to grow to 2.6 billion in the next 5 years. These numbers show that wireless subscriptions have already surpassed the number of internet users (expected to top 1 billion by mid-2005) and will represent a 37% penetration rate of the entire world population by 2010! To support this growth, wireless infrastructure deployments will also have to experience tremendous growth during the next few years.

Even with this growth, the wireless infrastructure industry can still be classified as entering a mature life cycle phase as we are beginning to see … Read More → "The Programmable Base Station"

If March winds bring April showers, then April showers must somehow give rise to new announcements in programmable logic and structured ASIC. From tools to technology to applications, let’s sail through some of the most interesting announcements this week to pick up on the latest trends. There continue to be significant advances in the design tools, silicon technology, and applications for FPGAs and customizable logic devices. A close look at this week’s news serves to highlight the direction that the industry is currently taking.

As FPGAs continue their migration from glue logic devices to central … Read More → "Mayday Mayhem"

For years it was like a slogan. “FPGAs are nice, but they’re power hogs.” For the customers that kept the lights on, however, buying thousands of FPGAs for backplane-based, rack-mounted equipment with monster power supplies and plenty of cooling, considerations like performance, I/O, and density far outweighed power as a design-in concern. If a new FPGA family offered a 50% performance increase or doubled the LUT count over the previous generation, damn the heatsinks and full-speed ahead. Designers rolled FPGAs in with reckless abandon.

Today, however, forces are conspiring to bring power concerns off of the … Read More → "Power"