Just out of college and needing some extra cash during the holidays, I worked briefly for a high-end haberdashery in Virginia. During orientation, we learned the tricks of the trade, including how to tie the perfect tie (I can still perform this impressive parlor trick…) and how to fold and stack dress shirts. But tucked neatly among all the expensive men’s clothing presentation skills was an actual life lesson. We were coached that we must not judge any customer by his appearance, and that some of the most important clients to visit the store would look … Read More → "This Engineer Walks Into a Bar…"

You know what they say about technophiles: Give us a wireless inch and we’ll take a wireless mile. Actually, make that a wireless metropolitan area network. It seems like only yesterday that we were content, even ecstatic, with a wireless network in our homes. Then we said, “Hey, if only we could use our wireless technology while drinking coffee in a small cafe, our lives would be complete.” Once we got a taste of non-fat, grande, double-shot Internet espresso, we wanted to put our coffee in a to-go cup, move our laptop applications … Read More → "Beverly Hills 802.16"

For years, we’ve talked about how FPGAs have the potential to accelerate digital signal processing (DSP) algorithms, producing higher performance with lower cost and lower power consumption than traditional DSP processors*. Whoa! Did you see that – the asterisk at the end of that claim? It’s true, though. Using the parallel computing capability of a typical DSP-enabled FPGA (one with hardware multipliers, MACs, or DSP accelerators) you can get tens to hundreds of times the throughput of a DSP processor running the same algorithm in compiled C code*. Hey! There it was again!

That … Read More → "Erasing the Asterisk"

Innovations within one domain of electronic product design typically have an unforeseen impact on other areas. For instance, innovation within FPGA devices that has enabled increased functional complexity and I/O performance has introduced challenges downstream during PCB design. Increased functional complexity has resulted in increased I/O pins per device and increased package pin density. In addition, increased I/O performance has resulted in a tighter set of PCB interconnect constraints to minimize degradation of high-speed signals as they travel between devices. The ability to leverage FPGA I/O flexibility to optimize FPGA/PCB performance offers significant value, … Read More → "Design Challenges Flow Downstream"

Content and concept are an interesting combination. People read FPGA and Structured ASIC Journal each week to learn from its content – articles, announcements, analysis, advertisements, and alliteration — all of them working together to inform and entertain engineers interested in programmable logic and structured ASIC design. Interestingly, it turns out that there’s a lot we can learn about programmable logic from FPGA Journal’s concept, too. That’s because FPGA Journal is to technical publications what FPGAs are to system design – highly flexible, fast to market, field programmable, field upgradeable, and at … Read More → "Field Programmable Journalism"

Geologic time is difficult for humans to visualize. Great continents slamming into each other with epic force, reshaping the earth’s surface, don’t seem so impressive when the movement is slowed down to an almost imperceptible rate. The only time we notice the effect is when transients like earthquakes, tsunamis and volcanic eruptions hint at the unwavering determination of the underlying forces. As electronic designers, however, we have some facility in dealing with alternate orders of magnitude in the time scale. We understand that nanoseconds and milliseconds are worlds apart, even though, as humans, we can& … Read More → "Tale of the Tools"