My twenty-three-year-old eyes couldn’t muster the maturity to disguise my frustration. He sensed their weakness. It was what he was watching for. Even as I struggled in vain to regain my composure, he moved in for the kill. “What did you say again that your company does?” My father posed the question, fully aware of the answer, waiting with the patience of the hunter who has already cornered his prey for my inevitable self-destruction.

I rolled into my own defeat with the resignation of a mortally wounded rabbit. “Gate arrays,” I … Read More → "What Do You Tell Them?"

The new generation of FPGAs with DSP resource and embedded processors are attracting the interest of the image processing market. With enhanced capabilities most of the DSP processing work can be off loaded from the software program stack to embedded processors and DSP resources on the FPGA to improve performance and reduce the cost of the whole system.

The traditional way of implementing algorithms in software limits the performance because the data is processed serially. Frequency of operation can be increased up to a certain extent to increase the performance or the required data rate … Read More → "Image Processing Applications On New Generation FPGAs"

It slices, it dices, and it has flash-memory. It gets your whites whiter, removes those collar rings, and flaunts flexible FPGA fabric. It has more flavor, is less filling, and boasts programmable analog to boot. It softens your hands while you do the dishes and offers a wide selection of pre-configured IP. Now how much would you pay? Well don’t answer that because now, Actel’s already incredible versatile Fusion programmable system chips also pack an available ARM7 processor.

Actel’s claims about Fusion sound like something from one of those impossibly overblown … Read More → "Fusion Adds ARM"

Over the past couple of years, the notion of Structured ASIC and Platform ASIC architectures, let’s refer to both as Structured ASICs, have received a lot of attention from the chip industry. Structured ASIC proponents tout the concept as a way of getting near-ASIC performance and unit pricing without the high NREs and long and complex design cycles of ASICs. On the other side, skeptics dismiss Structured ASICs as a ploy to save what they consider to be a dying ASIC design industry. In reality, the benefits of Structured ASICs lies somewhere between these two viewpoints – exactly … Read More → "Think You Know Where Structured ASICs Belong?"

Just three weeks ago, Xilinx announced the latest version of their PlanAhead software, asserting among other things that they had simplified the daunting task of partial reconfiguration. We listened, and went so far as to include a section on this potentially ground breaking technology in our February 7 article on the subject (see article). We acknowledged our hesitation to get too excited about the idea, feeling that it would take a very brave soul indeed to jump in and give it a try. At the time, it felt like the equivalent of … Read More → "SDR Prêt-à-Porter"

FPGA and PCB design teams have begun to leverage the flexibility of FPGA devices to create complex systems while optimizing their PCB design for performance as well as manufacturing costs. The immediate pay-off is a substantial decrease in design cycle time, from weeks to minutes while at the same time eliminating design risks associated with late design changes. The business critical benefit is pure cost savings derived from optimizing the PCB manufacturing process. There are a number of PCB manufacturing optimizations possible as a result of tuning the FPGA/PCB interfaces:

In the good old days, there was just one kind of FPGA – the “big” kind. Big is in quotes, of course, because even today’s most modest, miserly devices are bigger and faster than the best we could muster a decade ago. However, as the high end of FPGA technology rode the rocket of Moore’s Law toward the sky, becoming a viable solution for more and more complex applications, a new creature was born – the low-cost FPGA.

The concept seemed simple enough – “normal” high-end FPGAs were optimized for performance. Nothing was held back … Read More → "Upping the Low-Cost Ante"