Despite some popular speculation, “DAC” does not stand for “Declining ASIC Commiseration.” The Design Automation Conference is a robust and lively gathering of companies, customers and comrades sharing a common interest in the progressive automation of the electronic design process. As we’ve discussed the past couple of weeks, however, the historical focus of DAC has been on the custom and semi-custom digital IC design process. Sure, there have always been other disciplines and interests represented, but the money, the momentum, and the fear have always been centered around the completion of complex IC designs and the … Read More → "FPGAs at DAC"

The 43rd annual Design Automation Conference (DAC) got underway yesterday in San Francisco, California. The technical sessions have begun, the exhibits are open, and the parties, PowerPoints and pejoratives have now commenced. Last night, at a media, analyst, and customer briefing dinner at the San Francisco Museum of Modern Art, Walden Rhines, Chairman and CEO, hosted a customer presentation explaining how Mentor’s new Caliber nmDRC accelerates nanometer design rule checking by “hyperscaling” – a technique that takes efficient advantage of multiple processing elements to deliver many times the previous performance in giant DRC runs.

… Read More → "Electronic Elitism"

Exactly 299 days before “Cramming More Components onto Integrated Circuits” was published in Electronics Magazine, the first workshop of the SHARE Design Automation Project was held in Atlantic City, New Jersey. The SHARE workshop had papers with titles like “A method for the best geometric placement of units on a plane” and “Design automation effects on the organization.” The magazine article began with the statement “The future of integrated electronics is the future of electronics itself.”

With such generic paper titles and such an auspicious article intro, what has transpired since then that has inexorably linked those two … Read More → "DAC Previsited"

He pauses for exactly the right amount of time, then whips into his delivery with energy and zeal – “Have youuuuu been struggling to meet ever-tightening design schedules with more complex designs and a smaller, leaner design team?” He picks up the pace, enunciating each word with perfect clarity. “Do youuuuu find that the RTL methodology is too cummmmmbersome for today’s more sophisticated FPGA designs?” He widens his eyes as he meets the gazes of each member of the audience, conveying an ominous fear. “Are youuuuuuu suffering the pain and ravages of MOORE’s LAW?!?”

The … Read More → "System-Level Sideshow"

Every time FPGAs hit a new process generation, there is a buzz. People want to hear about the underlying architecture, learn how fast the new devices will go, guess at how much logic they’ll hold, speculate on whether we’ll need a small nuclear power plant to operate them, and marvel at marketing’s ability to take something already quite impressive and exaggerate it to the point where we have no idea what it can actually do. We tingle with excitement. We wait a year until actual devices are available. Then, when the magic moment comes and we … Read More → "Tooling up for 65nm"

Engineers are trained problem solvers. While various fields of engineering require different types of technical training and expertise, the techniques of problem solving are universal to all branches of the profession. If engineers are problem solvers, could one infer that reverse engineers are problem creators? In a narrow view, probably so – but reverse engineering has its place in the innovation cycle as well. Reverse engineers also help us hone our security skills to prevent attacks from those who wish to do us (and our design IP) harm.

Reverse engineering is not a back-alley, cloak and dagger, … Read More → "Logic Lockdown"