Taming Embedded Multi-Core on FPGAs for Packet Processing
In public discussions about embedded multi-processing and FPGAs, most of the focus has been on DSP. But there’s another application area requiring embedded multi-processing that has remained elusive, not because of silicon deficiencies, but due to the lack of an easy methodology. That application is packet processing. Packet processing performance as high as 10 Gbps is possible in FPGAs, so the silicon is fast, but even single gigabit performance has required RTL and a hardware approach to design.
Many companies with projects involving packet processing work exclusively in software, predominantly C. They have infrastructures and methodologies … Read More → "Taming Embedded Multi-Core on FPGAs for Packet Processing"