Complex ASIC Timing Verification Converges with FPGA-Based Designs
Over the past few years, as FPGA devices have increased in density, speed, and started embedding dedicated memory, multiplier blocks, high performance intellectual property (IP), PLLs, and high-speed SERDES, they have become a viable alternative to implement complex designs and applications that traditionally targeted ASIC or ASSP-based designs . This trend however is stressing the limits of traditional FPGA static timing analysis tools and designer productivity is affected.
To meet market requirements and achieve target performance, FPGA design engineers are adopting new design styles and complex clocking schemes (i.e. clock multiplexing in 10M, 100M, 1G … Read More → "Complex ASIC Timing Verification Converges with FPGA-Based Designs"