Articles – Page 556

January 30, 2007

For system designers, Moore’s Law is a gravy train. Every couple of years, you get more gates, more speed, less power consumption, and lower cost. For digital designers and tool developers, however, that gravy train is headed through the tunnel right at you. Every couple of years, you have more gates to design in less time, more complexity to overcome, and tougher verification problems. Your design tools are heavily impacted, too. The old synthesis and place-and-route runs that took a few minutes on an old 200MHz Windows 98 laptop are now running for 24 … Read More → "ISE Storm"

Actel Activates Platforms

Roadmap Solidifies Embedded Processor Strategy

by Kevin Morris

January 30, 2007

FPGA-based system-on-chip platforms are the etch-a-sketches of embedded design. You can quickly sketch out your embedded computing system, use it, and easily erase and re-construct it in place as design changes are required. Need a different peripheral? No problem, just reprogram it. Need to change a protocol – another simple hardware and software modification. Want to use a different processor core – or an additional one? Just drop it in and re-program the chip. Your same board keeps right on working.

Actel is the alternative FPGA supplier. On the … Read More → "Actel Activates Platforms"

Soft Processing and Customizable IP Enable Flexible, High Performance Embedded Design

by Kevin Morris

January 30, 2007

Which would you prefer for your next embedded project: flexible system elements so that you can easily customize your specific design, or extra performance headroom in case you need more horsepower in the development cycle? Why should embedded engineers put themselves under undue development pressure and settle for one or the other? Soft processing and customizable IP offer the best of both worlds, integrating the concepts of custom design and co-processing performance acceleration into embedded design.

Embedded engineers often struggle with the challenges of improving performance or changing system characteristics after they have already completed the general … Read More → "Soft Processing and Customizable IP Enable Flexible, High Performance Embedded Design"

Prototype to Production

Lattice Launches FreedomChip

by Kevin Morris

January 23, 2007

From about the time of the announcement of their foundry partnership with Fujitsu, Lattice Semiconductor has been doing things a little differently. Step by step, they’ve been establishing a real, credible presence in the fast-expanding FPGA market. Prior to that, their FPGA-related efforts had been less than stellar, and the company had survived on a strong heritage of CPLD offerings.

After establishing an FPGA beachhead with a competitive array of 130nm low-cost FPGA families, the company shoved their way into the elite 90nm FPGA race with a full line of well differentiated low-cost … Read More → "Prototype to Production"

DRM To Go

Discretix Locks Down Handsets

by Kevin Morris

January 23, 2007

Convergence is a cool concept. As embedded systems designers, once we’ve got a versatile computing platform constructed inside a mobile device, it’s exciting to think of all the plus-ones we can add by including plug-in software modules, small incremental pieces of hardware, or plug-and-play peripherals through standardized interfaces. The conceptual leap from mobile phone to PDA to media player is pretty small once you start down the path.

Unfortunately, slapping on the cool new features isn’t always the tricky part. Before your customers can lounge out listening to … Read More → "DRM To Go"

FPGA’s Final Frontier

Programmable Logic at CES

by Kevin Morris

January 16, 2007

It is the final and biggest frontier for field programmable gate arrays. FPGA companies jumping into the gargantuan consumer electronics market – estimated at over 135 billion dollars this year in the US alone – may find it’s like swimming from a fishbowl into the ocean. Although the programmable logic pecking order may have been well established back in the home aquarium, jumping out into the big sea changes the rules dramatically.

In this new domain, where trade shows like the Consumer Electronics Show (CES) count their attendees with six digits despite restricting … Read More → "FPGA’s Final Frontier"

Consumer Electronics Show 2007

Embedded Reporting from the Front Lines

by Kevin Morris

January 16, 2007

The Consumer Electronics show is so large that it’s small. Amidst the acres of exhibits and over 140,000 attendees, the topics and interests are so diverse that the event becomes a buffet of sorts, serving up a greater variety of technology than you can find anywhere in the world, but specializing in nothing. Few of the companies exhibiting here consider CES their “big show” of the year. That status is reserved for the more specialized shows that go into exhaustive detail on any of the sub-subjects sampled at CES.

Total Recall

Synplicity Innovates in Verification

by Kevin Morris

January 9, 2007

They say that history repeats itself. Unfortunately, however, we find that this is often not true in debug mode. That elusive set of conditions that precipitated the problem we’re pursuing often fades into obscurity when we try to capture, observe and analyze them. Take, for example, the problem of debugging system-on-chip ASIC designs or any complex hardware system where massive quantities and varieties of real-world stimuli are required to give your design the thorough shaking-out it needs to capture that once-in-a-blue moon bug in the act. In that case, there’s a … Read More → "Total Recall"

Conspicuous Consumerism

CES Takes Over Vegas

by Kevin Morris

January 9, 2007

The Consumer Electronics Show (CES) debuted in 1967 – shortly, it turns out, after Gordon Moore made the prognostication that has come to be known as “Moore’s Law.” This week, in Las Vegas, CES is celebrating its 40th anniversary. So how is the old show doing? In those 40 years, the number of exhibitors has risen from 110 to over 2,700, and the show space has grown by over 11X. The number of attendees has mushroomed to well over 100,000 (estimates are around 140,000 for this year’s show). It proudly proclaims that it is … Read More → "Conspicuous Consumerism"

Power Exploration in High-Level Synthesis

by Kevin Morris

December 19, 2006

Area optimization and timing closure have long been considered the most common digital design challenges in mainstream digital IC design. Much has been analyzed and documented on how to solve these issues at the various design levels – from RTL to gate to layout. In recent times however, as design applications have become more portable and power sensitive, power exploration and smart design practices for optimizing power have taken centre stage.

Abstraction Facilitates Design Optimization

First, let’s review the benefits of high-level synthesis. As … Read More → "Power Exploration in High-Level Synthesis"