They say that history repeats itself.  Unfortunately, however, we find that this is often not true in debug mode.  That elusive set of conditions that precipitated the problem we’re pursuing often fades into obscurity when we try to capture, observe and analyze them.  Take, for example, the problem of debugging system-on-chip ASIC designs or any complex hardware system where massive quantities and varieties of real-world stimuli are required to give your design the thorough shaking-out it needs to capture that once-in-a-blue moon bug in the act.  In that case, there’s a … Read More → "Total Recall"

Area optimization and timing closure have long been considered the most common digital design challenges in mainstream digital IC design. Much has been analyzed and documented on how to solve these issues at the various design levels – from RTL to gate to layout. In recent times however, as design applications have become more portable and power sensitive, power exploration and smart design practices for optimizing power have taken centre stage.

Abstraction Facilitates Design Optimization

First, let’s review the benefits of high-level synthesis. As … Read More → "Power Exploration in High-Level Synthesis"

Every year, we put on our historian hats and look back at the events of the previous twelve months.  (It turns out that our historian hats are orders of magnitude more accurate than our future-predicting goggles, by the way.)  This year, the industry continued an inertial growth trend in both the technology and business axes.  OK, there.  We’re done.  You can stop reading and head off to celebrate whatever holiday your particular culture observes this time of year — even if it’s just international “the office is closed for a … Read More → "Dangling Propositions"

Your boss begins to drone on about the system maintenance check list items during your weekly meeting.  Power initialization and sequencing, reset management, voltage and current monitoring, system clocking, data logging, remote communications, diagnostics and prognostics, SRAM field-programmable gate array (FPGA) management, errors and alarms, thermal management, ID and authentication, and microcontroller (MCU) boot loading. Just before you nod off in perfect sleep, you hear the words “critical,” “operational” and “job in jeopardy”…

The above is a collection of seemingly unrelated tasks with the goal of ensuring … Read More → "System Management – Not Sexy, But Critical"

“FPGA’s at this price point offer an unprecedented value, and are an excellent strategy to future-proof your design with.”

Shirley stares at the sentence glowing from her Dell monitor for a minute and sighs, then she stretches as she looks out her office window at the distant San Antonio skyline.  The publication deadline is rapidly approaching and the article needs serious work.  There is too much wrong with this one sentence to even mention – dangling preposition, comma separating dependent clauses in a compound predicate, possessive form of “FPGA” … Read More → "A Techfocus Tribute"

Today’s fast-paced chip delivery schedules require that logic designers employ design flows that are versatile enough to take advantage of several implementation technologies. Specification changes, pricing or yield issues, and production ramps can change the target implementation technology for a design. Designers might be required to change FPGA devices or vendors, or move their designs from prototyping in an FPGA to production with an ASIC.

Making a decision on whether to use FPGAs or ASICs is based on several requirements including performance, power, unit volumes and time to market. In some cases, FPGAs are used … Read More → "Unified FPGA-ASIC Design Flow Provides Designers Versatility in Meeting Production Goals"