The sculptor Auguste Rodin was asked how he created his amazing statues.  He replied, “I choose a block of marble and chip off whatever I don’t need.”  Michelangelo is also sometimes attributed with a similar quote.  “I saw the angel in the marble and carved until I set him free.”  These two quotes are probably the origin of the well-worn story about the sculptor who, when asked how to carve a statue of a horse said, “I simply chisel away everything that doesn’t look like a … Read More → "Altium’s Alternative"

If you own a Cajun cookbook, you may have noticed that virtually every recipe begins with this step.  If you can’t make a Roux, you can’t cook Cajun.  The recipe for Roux (if you can find one) is always fairly vague – “Put some flour and oil in a pot and heat until the color changes to brown.” How much flour?  How much oil? How much heat? What shade of brown?  All of these questions are, as we learned in engineering school, “left as an exercise for the … Read More → "First, Make a Roux"

This week, at the Design Automation Conference (DAC) in San Diego, FPGA tool specialists Synplicity announced the acquisition of the Swedish company Hardi Electronics – supplier of FPGA-based prototyping boards.  Why is this interesting?  It gives us a number of insights into the increasing role of FPGAs in system-level verification, the complex nature of the tools market for FPGAs, and the volatility of the EDA business in general.

FPGAs have long been used as prototyping vehicles for ASIC designs, ASSP designs, board-based system designs, and of course for FPGA-based designs.  As a long-time leading … Read More → "FPGAs at DAC"

High-speed system interconnects have a large impact on integrated circuit (IC) package design. High-speed connectivity requires fabrication of packages that are able to support very fast varying, broadband signals with good signal integrity (SI).  Based on Moore’s law, on-chip clock frequency doubles every 18 months and the intrinsic delay of the gate decreases exponentially to a few picoseconds (ps). Increasing I/O counts add another element to this equation. Rent’s rule states that the number of I/O will double in the next ten years, which means that there will be a lot … Read More → "FPGA Packaging and Signal Integrity"

Don’t be fooled by quarterly results.

Lattice Semiconductor has been on a new-product rampage for the past two years.  Beginning with their alliance with foundry partner Fujitsu, the company has put up an impressive streak of successful new product introductions.  From the company’s first low-cost FPGA, the “El Cheapo” Lattice EC, to the just-introduced XP2 90nm non-volatile family, Lattice seems to have gotten its engineering act together in a big way.

Why haven’t their financial results shown it yet?  In the FPGA business, the … Read More → "Lattice Leaps Forward"

For years, we had just “FPGAs.”  We didn’t have today’s high-end, low-cost, value-based, platform-enabled, I/O optimized, low-power, DSP-enhanced, SerDes-enriched flavors.  The very nature of FPGAs was to be generic.  They were, after all, reprogrammable devices that could tackle any task assigned to them (provided, at the time, that task didn’t require more than about 30MHz performance or more than a few thousand look-up-tables or any memory or even the merest modicum of power efficiency.)  In other words – glue logic.

From those humble beginnings, … Read More → "Merging Lanes"