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Bringing Reality to PCB Design

In a fundamental shift that redefined how products are created, the transition of engineering design from manual drafting-based methodologies to Computer-aided Design has transformed design in virtually all branches of engineering. The application of CAD in the electronics industry is no exception, and has revolutionized the way engineers work and the products that can be developed. You won’t find too many engineers that would be willing to go back to the old methods.

What you would be going back to is laying out strips of tape and sticking graphics shapes on a flat sheet to … Read More → "Bringing Reality to PCB Design"

Embedded World

Embedded world was always big. Now it is enormous. Nearly 700 companies were exhibiting there this year (twice the number booked for ESC in San Jose next month), with over 17,000 visitors.  Just think – if I spent half an hour talking to each exhibitor, and that is a journalist’s schedule for an average interview, allowing for 40 hour weeks, and not including lunch, coffee and comfort break, it would take nearly nine weeks just to meet everyone.  Nor does that include the press conferences, which normally demand an hour of attention, nor the conference that ran for … Read More → "Embedded World"

Migrating Complex Networking ASIC Verification Environment to SystemC and SystemVerilog

Introduction

As the computer hardware industry strives to obey Moore’s Law, the telecommunication industry is following the even more rapid phenomena as described by Metcalfe’s Law: the potential number of contacts between each end computer increases rapidly, the effort to reduce the congestion at the network layer is greatly contributing to today’s system-on-chip (SoC) complexity.  As more and more optimizations are added to the upper layer protocols, low layer complexity increases to facilitate overall system feasibility.  Over the past decade, we have witnessed a dramatic increase in … Read More → "Migrating Complex Networking ASIC Verification Environment to SystemC and SystemVerilog"

When Being One-Dimensional Is A Good Thing

Driving in the country and in the city are completely different experiences. In the country, there’s so little traffic that you really don’t need much in the way of rules. Roads intersect, maybe with a stop sign, maybe not; it’s expected that you will look as you approach and proceed with caution (unless you’re the Dukes of Hazzard). If people start moving into the area and the traffic gets busier, then at least one of the intersecting roads will need a stop sign to avoid outright chaos. If things … Read More → "When Being One-Dimensional Is A Good Thing"

Comparing Power Consumption of FPGAs with Customizable Microcontrollers

Introduction

As transistor technology quickly shrinks toward the vanishing point, embedded devices are taking over the marketplace.  One of the key challenges of designing an embedded electronic device is maintaining reasonable power consumption in order to maximize battery life.  For design engineers wanting to combine the functionality of a microcontroller with their own “special sauce” logic, a standard off-the-shelf microcontroller plus Field Programmable Gate Array (FPGA) combination has long been the preferred option. 

Despite the ease of use and availability of FPGAs, they are notoriously power hungry and … Read More → "Comparing Power Consumption of FPGAs with Customizable Microcontrollers"

Maximizing Your Millimeters2

FPGAs have always benefited from the rising waterline of Moore’s Law.  When the first programmable devices hit the market, the price of programmability was very high.  The amount of density, power, and performance you gave up to gain the privilege of programming your hardware on your desktop or in your system was so large that only a few specialized applications could justify the programmability penalty.  As process nodes passed, however, Moore’s Law worked in our favor.  As transistors got cheaper, faster, and thriftier on power, the relative disadvantage of FPGAs disappeared … Read More → "Maximizing Your Millimeters2"

Seeding Multicore Infrastructure

Seeding a saturated solution for optimal crystal growth can be a tricky business. The highest-quality, largest crystals grow when given lots of time for the molecules to orient themselves in the lattice. Seeding too late can result in chaotic explosive nucleation, small granularity, and low quality. Seed too early, and, well, there may not technically be a problem, but being an impatient species, if we don’t see crystal growth quickly enough, we tend to get bored and move the seed elsewhere.

Saturation is something of a measure of potential, of pent-up … Read More → "Seeding Multicore Infrastructure"

Do Converging Standards Meet at Infinity?

Accellera’s chair, Shrenik Mehta, of Sun, has no truck with the traditional standards process. His view is that it is important to get a standard accepted and in use as soon as possible, particularly in the EDA field. Accellera’s name reflects this, and its method of working is designed to achieve it.

Accellera membership is a mix, reflecting its mission statement which is:

Drive the worldwide development and use of standards required by systems, semiconductor and design tool companies that enhance a language-based design automation process.

</ … Read More → "Do Converging Standards Meet at Infinity?"

A Merger of Unequals

As the orks circled the tower in growing numbers, efforts to finish the weapon became increasingly frantic. The mechanical portion was almost complete: all of the strength and stress tests had passed, so the structure was ready to go. They had done practice shots with weights equivalent to the final payload, and distance and accuracy looked good. They fiddled a bit more with the pivots and joints to make sure that wear wouldn’t be excessive. But the real thing they were waiting for was the payload itself. This was a mystery concoction brewed up by some tall mysterious … Read More → "A Merger of Unequals"

Making FPGAs Cool Again – Part 2

A couple weeks ago we looked at the state of FPGA low-power design from the standpoint of hardware. We saw a range of features, from very little to branded feature sets. But none of that matters without tools: tools are the window into the silicon, and no silicon feature has a shred of value unless a tool uses it (as can be testified to by the scores of now-defunct PLD businesses that were run by “the cheapest silicon always wins and software is annoying” types). And with a domain like low-power design, the tools can … Read More → "Making FPGAs Cool Again – Part 2"

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