When it comes to successful FPGA implementation, synthesis serves as arguably the most influential step in ensuring that design requirements are met and the product can be shipped. In many cases, design requirements refer to performance and area—the design needs to operate at a minimum frequency and it needs to fit into the selected device. Hence, designers or CAD managers looking to standardize on a synthesis tool tend to look for good out-of-the-box quality-of-results (QoR).

The criteria for selecting the right synthesis tool, however, can—and should—be involve more than this. Adequate … Read More → "Selecting the Right FPGA Synthesis Tool"

How fast?  Try 1.5 GHz.

Now, I know what you’re thinking…

“offer void where prohibited, professional stunt engineer on closed-course benchmark – do not attempt, your frequency may vary, dealer participation may affect final negotiated performance, operating frequency is not valid in North Dakota, Florida, Alaska, Hawaii, or at any location with ambient temperatures above 24C, performance graph not to scale, preliminary datasheet, results not typical…”

Well, before you go inventing all your own “fine print” for why a large-capacity FPGA fabricated on … Read More → "Fast. Very, Very Fast."

The applications space for the PCI Express standard continues to expand tremendously as it becomes more commonplace in PCs and other systems where inexpensive, high-speed interconnect is required.  In order to meet the demands of this growth, a plethora of systems solutions intended to get designers up and running quickly with PCI Express have been developed by a growing number of hardware and software vendors.  As a result, designers often are faced with a bewildering number of choices when creating and implementing PCI Express-based add-in cards or systems.  These choices include the width of … Read More → "Comparing Low-Cost SERDES-Based FPGAs to ASSPs for PCI Express System Design"

Today’s high-performance, multi-core processing systems are complicated beasts – from both a hardware and a software perspective.  Developing the architectures, protocols, interconnects, and software development tools and methodologies that can take advantage of multiple 64-bit processors working in collaboration can’t be done on a chalkboard.  It’s an exercise that requires extensive prototyping, trial-and-error, and experimentation. 

Unfortunately, “experimenting” with implementations in monolithic silicon is impractical for any of us that don’t moonlight managing hedge funds.  When there is a seven-figure price tag and a few months of turnaround time for each “ … Read More → "Sun Shines on Xilinx"

We’ve all had a fun time complaining.

It’s not like Marketing (upper-case “M”) was without blame, either.

When the new millennium dawned, we’d had enough of “System Gates” – the metric that FPGA companies used to describe and inflate the capacity of their devices.  In those days, vendors gave us a huge number – something like the number of transistors divided by three or four, as the “system gate” count of their devices.  Most of the transistors on an FPGA, however, are involved in configuration logic, routing, and other structures that don’ … Read More → "Apples to Apples"