“You’re ready for tape-out already??”
“Yup!”
“Um… “ “And it meets all specs? In all corners and modes?”
“It should.”
“What do you mean, it should?”
“Well, we designed it to where it should. Of course, once we get silicon out, we can try it out and see if it all works. If not, well, we’ll make some tweaks and try … Read More → "Starting From Scratch"
Software development processes can vary dramatically. If you program only occasionally as a hobby, like me, then you dream up what you want to do and immediately start coding. Working units then randomly materialize and just as quickly disappear like quantum fluctuations. Moving into the more professional arena, if there is a process, it can vary from something light, agile, and extreme, where code is generated quickly and converges towards requirements using Brownian successive approximation, all the way to heavyweight rational processes with which you risk spending your entire career just reading the manual (understanding it would take even … Read More → "Disziplin Muß Sein*"
Building on commodity hardware and industry standard software programming methods, Baylor group architects a $10,000 reconfigurable computing cluster.
Accelerated computing – using programmable logic and other non-traditional processing resources to augment clusters – has become increasingly popular. Most recently, the NSF announced that $20,000,000 in funding is available for research groups to push beyond petascale computing. Accelerated computing represents the leading edge of the high performance computing wave, as evidenced by the world’s fastest supercomputer, the Roadrunner cluster located at Los Alamos National Labs. Roadrunner makes use of commodity processors coupled with … Read More → "Low Cost Reconfigurable Computing Cluster Brings Millions of Reconfigurable FPGA Gates to Students"
According to Gartner’s Jim Tulley, there are around 7,000 ASIC design starts a year, a number that is in slow decline. By way of contrast, there are around 100,000 FPGA design starts a year, of which 30,000 include a microprocessor of some kind. Yet for eleven years at the IP conference in Grenoble, the leading get-together for IP suppliers and users, the only mention of FPGAs has been in the context of building blocks for ASIC prototyping tools or, more recently, for testing the market before undertaking the incredibly more costly task of building an ASIC.
Obviously, … Read More → "IP for Complex FPGAs"
If you had all the time in the world, you could simulate an entire SoC using SPICE, but you don’t, so you can’t. At least not for digital circuits; analog is different, since detailed analysis is required there, and it’s not a billion transistors. And yet, even with digital, we can’t quite revert all the way to 1s and 0s, but we can start to use some abstraction in the form of library cells for basic circuit chunks like transistors, inverters, gates, and flip-flops. Those cells can be characterized using SPICE ( … Read More → "Uncanny Resemblances"
A few weeks ago I wrote about model-based development in Modelling: not just for big boys? At the end of the article I said “So is modelling just for big boys? Well, I hate to say it, but unless companies change their views on an appropriate level of expenditure for tools, yes it is, today. However, I have heard that one company is planning an announcement that could change this scenario quite markedly. And if the rumour is true, there may soon be a tool that will … Read More → "Is Free Too Good to be True?"
We engineers are unusually comfortable with periodicity. We find ourselves fooling around with frequency domain from the first days of our undergraduate education, and by the time we become practicing professionals, we whip in and out of Fourier’s follies with the facility of wild monkeys traversing the forest canopy. We eat, drink, and breathe periodic waveforms. We handle harmonics, passbands, s-planes, and corners with reckless abandon. We own the spectrum.
When it comes to our own careers, however, some of us switch to DC … Read More → "Deep and Wide"
If you were able to record the development of a town as it grew into a city over years and decades and then speed up the film in a super-fast-mo replay, you’d notice, assuming you weren’t thrown into an epileptic seizure by the rapid day/night flashing, that things start in a small center and move out for a while. Farmlands are replaced by tract homes, forests are cut down, hills may be leveled or developed, and the town inexorably creeps outward like mold in a Petri dish.
At some point, a limit … Read More → "Getting Around Limits By Getting High"
There is an old story about two shoe sales people sent to a desert island. The first looks around and sends a message back to head office, “No one here wears shoes. Coming home on next ship.” The second sent a message to his head office, “No one here wears shoes. Send several hundred pairs on next ship.” The mood at the Paris International Automotive Electronics Congress (IAEC), earlier this month, was more like that of salesman two. The tribulations of the mainstream auto market, particularly the US, was recognised, but the view was that … Read More → "Toys for Engineers in Automotive"
Design reviews conger images of engineers carrying reams of code printouts, filing single-file and head down into a room to be judged by others. The positive impact of design reviews has been proven though many studies, but does the preparation and process of the review have to be so painful? This paper provides a practical approach to design reviews that soothes the process and actually results in a positive experience.
The key to a painless design review process is to use techniques and tools as code is developed that contribute to a quality solution, minimizing the time … Read More → "Minimizing the Pain of RTL Design Reviews"
