Making sure the hardware version of your DSP algorithm is doing what you want can be a difficult task – particularly if you are doing high-performance algorithms that require hardware accelaneration in FPGAs. </ … Read More → "CHALK TALK – Simplified Verification of DSP Algorithms in Hardware"
Read More → "CHALK TALK – Power Estimation in High-Level DSP Design Flow"
Making sure the hardware version of your DSP algorithm is doing what you want can be a difficult task – particularly if you are doing high-performance algorithms that require hardware accelaneration … Read More → "CHALK TALK Simplified Verification of DSP Algorithms in Hardware"
Today’s complex, high-pin-count FPGAs present a special problem for board designers as issues of timing, routability, cost, and signal integrity … Read More → "CHALK TALK – FPGA – PCB Co-Design Done The Right Way."
Making sure the hardware version of your DSP algorithm is doing what you want can be a difficult task – particularly if you are doing high-performance algorithms that require hardware … Read More → "CHALK TALK Simplified Verification of DSP Algorithms in Hardware"
Making sure the hardware version of your DSP algorithm is doing what you want can be a difficult task – particularly if you are doing high-performance algorithms that require hardware … Read More → "CHALK TALK – Simplified Verification of DSP Algorithms in Hardware"
In this webcast, Amelia Dalton talks with Mark Moran from Xilinx about using low cost FPGAs to reduce total system cost in your next design. It turns out that saving money on the FPGA is … Read More → "CHALK TALK – Lowering System Cost Made Easy with Extended Spartan -3A Family"
Evaluating any EDA tool has several challenges. You have several tools and vendors to choose from. You have to get past the marketing hype to determine what is really important to you and whether the supported feature set meets your requirements. Finally, you have to make sure that the features you need perform as advertised. And, of course, you have to do this evaluation while juggling all your other tasks.
Evaluating … Read More → "Evaluating a Design Data Management System"
Last summer we took a look at the fact that formal verification is seeing something of a repositioning and resurgence. The holiest of holies is the ability to verify that all possible use cases of a piece of logic have been specified and that all possible outcomes of those use cases have been verified to operate as desired.
It can be viewed as a big jump from no formal verification to the complete set; it’ … Read More → "Acquiring More Addicts"
