Printed circuit board (PCB) design software is one of the oldest segments of electronic design automation (EDA).  Long before people were doing synthesis, formal verification, HDL simulation, or most of the other modern design automation processes, tools were around that helped us automate the design and layout of our PCBs.  Today’s PCB tools carry the legacy of that long history – both conceptually and, in some cases, literally.  Some of today’s PCB tools still carry pre-historic code that was developed long before… well, before FPGAs came along, for example.

Why should we care … Read More → "Mind the Gap"

The age of mainstream 40nm FPGAs has now arrived.  

Last May, Altera announced the first-ever 40nm FPGA family – Stratix IV.  Last quarter, that announcement became a practical reality as the company began shipping Stratix IV devices to customers.  Last week, in dueling announcements, Altera announced their second wave of Stratix IV devices, while Xilinx rolled out their new Virtex-6 and Spartan-6 families.  Across all of these announcements, one thing is clear.  The race for supremacy in the 40/45nm process node for FPGAs focuses on the proliferation of high-speed serial I/O.  </ … Read More → "Serial Soirée"

It’s all coming together.

In response to a rapidly broadening market and increasingly niched and specialized competition, the world’s largest FPGA company has narrowed and focused.  With the celebration of their 25th anniversary and the introduction of their new Virtex-6 and Spartan-6 lines, the company is demonstrating the principle of doing more with less – ironically solving a broader class of problems with a narrower range of solutions.

Of course, a lot of this consolidation actually takes place under the hood, where most designers may never notice.  As the company has demonstrated … Read More → "Grand Unification Theory"

It was crunch time – the end of the semester in EE school – early 1980s.  I, in my usual undergraduate fashion, had procrastinated and was now slamming a unit every day on my self-badly-paced logic design course.  The course was designed so that we could complete an average of a unit per week and finish within the semester.  Each unit had a section of the textbook to study, (such as “Karnaugh Maps”), a quiz to pass, and a lab to complete (like “verifying Karnaugh simplification using TTL logic”).  I had waited until there were exactly enough … Read More → "Breakout"