Many of us who wound up in engineering-related careers were fascinated with technology as kids. Whether we were reading about cars, airplanes, computers, or hi-fi gear, we were intrigued by the latest and greatest of whatever genre we were investigating. What was the fastest car – the biggest airplane – the most powerful sound system? The exotic and superlative held a special fascination, often manifest as posters hanging on our walls or as the topic of playground discussion. “Nuh-uh, the Lambo has a top speed of almost 200MPH – way faster than that lame-o Ferrari on your poster!” It& … Read More → "Superlative Soup"

As FPGAs increase in density, system designers are using these increased densities to the maximum by creating larger and more complex designs. These large designs are based on design requirements that either requires adding new functionality to an existing application such as a channel card or a line card used in wireless applications or reducing board real estate by combining the functionality of two chips into a single device or creating new designs for new applications.

These varied designs could contain … Read More → "How Physical Synthesis Enables FPGA Design Productivity"

The system is both elegant and enigmatic.

When visitors see the RocketDrive sitting on your lab bench (particularly if it is plugged into the handsome show-floor-worthy box currently making the rounds at trade shows), your “cool factor” will definitely creep up a notch or two. When you use it to help you knock bugs out of your next FPGA design, you’ll most likely be pleased with your purchase. GateRocket’s RocketDrive is a useful tool for FPGA designers.

You have to be careful, though, not to think about it too hard.

You … Read More → "GateRocket Blasts Off"

Introduction

Prototyping an ASIC, ASSP, or SoC onto a single FPGA is not without its challenges. You have to deal with differences in ASIC and FPGA architectures, optimize for performance and area requirements, and account for a debug strategy. Unfortunately, this is only the tip of the  iceberg when tasked with implementing an ASIC onto a multi-FPGA platform. Currently, the largest FPGAs have a capacity of roughly 1.5 M equivalent ASIC gates, so when prototyping a chip larger than this, a multi-FPGA strategy must be in place, and several more pitfalls must be accounted … Read More → "A Synthesis & Partitioning Strategy for Effective Multi-FPGA Prototyping"