According to Gartner’s Jim Tulley, there are around 7,000 ASIC design starts a year, a number that is in slow decline. By way of contrast, there are around 100,000 FPGA design starts a year, of which 30,000 include a microprocessor of some kind.  Yet for eleven years at the IP conference in Grenoble, the leading get-together for IP suppliers and users, the only mention of FPGAs has been in the context of building blocks for ASIC prototyping tools or, more recently, for testing the market before undertaking the incredibly more costly task of building an ASIC.

Obviously, … Read More → "IP for Complex FPGAs"

Design reviews conger images of engineers carrying reams of code printouts, filing single-file and head down into a room to be judged by others. The positive impact of design reviews has been proven though many studies, but does the preparation and process of the review have to be so painful? This paper provides a practical approach to design reviews that soothes the process and actually results in a positive experience.

The key to a painless design review process is to use techniques and tools as code is developed that contribute to a quality solution, minimizing the time … Read More → "Minimizing the Pain of RTL Design Reviews"

Altera has carved a unique niche in the market with their HardCopy ASIC offering.  As we all know, FPGAs offer some compelling benefits when compared with traditional ASICs – short design cycles, zero-NRE, and in-field re-programmability are the ones most often cited.  For low- to medium-volume applications, FPGAs can be a wise choice compared with a high-risk, high-NRE, low-volume ASIC run.

FPGAs are not a panacea, however.  Low-cost FPGAs don’t have the speed, capacity, or rich feature set of their high-end brethren.  If you need advanced capabilities, you’ll pay an advanced price, … Read More → "HardCopy in Practice"