Articles – Page 520

March 3, 2009

You can’t figure out whether it’s a bad dream or just a dream. You’re gliding down an escalator towards a large, subterranean space. All you see is black and white, as if color has been banished from the building. Despite your misgivings, the escalator delivers you into the monochromatic morass. Shoulder-to-shoulder suits explain the chromatic deficit. Interactions are formal, even stilted. Snippets of banter range from the banal to the arcane. You question whether you could cast a cogent contribution into any of the conversations, whether you really belong here. You pinch yourself; … Read More → "Braving the Black-and-White"

Simplifying DDR

Mentor’s New DDR Wizard

by Bryon Moyer

March 3, 2009

Over in one of our sister pubs, we did a review of some of the challenges of DDR last year. In particular, DDR3 has some incredible timing subtleties that have to be managed. DDR controllers are available as IP for FPGAs, but they still have to be connected to the memories on the board. And those board connections can seriously affect whether or not the timing requirements of the DDR protocols are properly met.

Mentor has just announced new versions of their HyperLynx PI and SI board power … Read More → "Simplifying DDR"

Free Linux Microprocessor*

(Some Restrictions Apply)

by Jim Turley

March 3, 2009

In keeping with our theme of free stuff (see Embedded Technology Journal, January 27, 2009) we proudly chronicle the newest free alternative for embedded developers: a free Linux-compatible microprocessor. Never has so much been offered to so many for so little. Or something like that.

Here’s the deal. Altera, the world’s second-best-known FPGA company, has struck a deal with Wind River Systems, the world’s second-best-known embedded-software company, to port Linux to Altera’s NIOS II processor. And since NIOS is free, … Read More → "Free Linux Microprocessor*"

Free Linux Microprocessor*

(Some Restrictions Apply)

by Jim Turley

March 3, 2009

FPGA – PCB Co-Design Done The Right Way (CHALK TALK)

by Jim Turley

March 2, 2009

Today’s complex, high-pin-count FPGAs present a special problem for board designers as issues of timing, routability, cost, and signal integrity … Read More → "FPGA – PCB Co-Design Done The Right Way (CHALK TALK)"

FPGA – PCB Co-Design Done The Right Way

by Bryon Moyer

March 2, 2009

Today’s complex, high-pin-count FPGAs present a special problem for board designers as issues of timing, routability, cost, and signal integrity can defeat old-school “over the wall” design flows.

In this Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence about about bridging the gap between FPGA design and PCB design.

Read More → "FPGA – PCB Co-Design Done The Right Way"

Solving Today’s Tough FPGA Design Problems

by Bryon Moyer

March 2, 2009

Are your FPGAs outgrowing your tool flow? Join Amelia Dalton as she talks with Jeff Garrison of Synopsys about setting up your design tools for today’s more demanding FPGAs.

We’ll discuss how the size and complexity of today’s FPGAs demand … Read More → "Solving Today’s Tough FPGA Design Problems"

CHALK TALK – FPGA – PCB Co-Design Done The Right Way.

by Bryon Moyer

March 2, 2009

Dual-Processor FPGA Designs Made Easier

by Bryon Moyer

March 2, 2009

Thinking of using multiple processors on FPGA-based systems? Join Amelia Dalton as she demystifies dual-processor development with Rey Archide of Xilinx.

The webcast explains how to manage the challenges associated with placing one or more processors in an embedded-system-on-FPGA. FPGAs are becoming very popular platforms for embedded systems designers, and Xilinx has a rich portfolio of tools and IP … Read More → "Dual-Processor FPGA Designs Made Easier"

CHALK TALK – Simplified Verification of DSP Algorithms in Hardware

by Bryon Moyer

March 2, 2009

Making sure the hardware version of your DSP algorithm is doing what you want can be a difficult task – particularly if you are doing high-performance algorithms that require hardware accelaneration … Read More → "CHALK TALK – Simplified Verification of DSP Algorithms in Hardware"