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Visibility Enhancement Technology Confronts the Visibility Issue with Full-Chip Simulation

When it comes to system-on-chip verification, two trends have become painfully obvious: it is expensive and it takes too long. Consider, for example, that the most expensive parts of today’s SoC design flow are the tasks where the engineer must engage in direct manual effort or expend energy making decisions. In the case of verification, far too much time and money are wasted on tasks that don’t add value, such as trying to figure out how supposedly-correct intellectual property (IP) is actually working, debugging “dumb” errors or deciding what signals to record in … Read More → "Visibility Enhancement Technology Confronts the Visibility Issue with Full-Chip Simulation"

Dueling DFMs

Design For Manufacturing (DFM) was a headline darling for a while and somehow disappeared off the radar, even as debates continued as to whether all the DFM fuss was about nothing. In fact, much of what constitutes DFM, originally implemented as point tools by young upstart companies, has quietly been subsumed into mainstream flows by mainstream tool providers, thanks in part to the traditional EDA start-up/buy-up cycle.

Fundamentally, design and verification have gone from modeling the idealized results of a manufacturing process to modeling the actual manufacturing steps in much greater detail. The criticality and accuracy … Read More → "Dueling DFMs"

Dhrystone Is Dead; Long Live CoreMark!

“There are lies, damn lies, and benchmarks.” With apologies to Mark Twain (or possibly Benjamin Disraeli or maybe Henry Du Pré Labouchère), benchmarks have been used and abused ever since there have been computers. Like the question about when the first auto race was held (“as soon as the second automobile was built”), the question of who makes the fastest computer has beguiled and bedeviled engineers for ages. Now, just maybe, we may be making progress toward settling that dispute.

The bigger the computer, the bigger the benchmark. Conversely, testing … Read More → "Dhrystone Is Dead; Long Live CoreMark!"

Atmel SAM3U Boasts Screaming USB

Atmel made its name with programmable logic and nonvolatile memory, but the company is now a big supplier of microcontrollers, too. It’s one of the earliest and oldest ARM licensees, and this week the company announced an interesting new ARM-based processor chip that might move Atmel to the front of your shopping list.

The new SAM3U chip (full name: AT91SAM3U) slots in between the company’s existing ARM7-based processors (SAM7) at the low end and its ARM9-based chips (SAM9) at the higher end. Atmel’s ARM7 chips have … Read More → "Atmel SAM3U Boasts Screaming USB"

Demonstrating Targeted ROI

Wall Street says, “Flat is the New Up!” GSA says, “Semiconductor sales for 2008 totaled $252 billion and dropped 6%, compared to 2007 sales of $268 billion.” California’s unemployment rate hit a record 11.2 percent in March 2009, allegedly the worst since the Great Depression! In our own world, EE Times reports: “The unemployment rate for all engineers jumped from 2.9 percent in the fourth quarter of 2008 to 3.9 percent in the first quarter of 2009, IEEE said.” And Nostradamus predicted the end of the world… For businesses, it’s all about increasing productivity, maximizing ROI, accelerating time to market, … Read More → "Demonstrating Targeted ROI"

A Nice DATE in Nice

I have to confess a weakness – I love trade shows/exhibitions. I enjoy being involved in designing, creating and setting up trade show booths, enjoy working on a booth and talking to new people, and enjoy walking the aisles and learning about new products and new companies, particularly at a crowded show where there is a special buzz. I believe that, when properly used, they are an efficient weapon in the promotional arsenal and can easily repay the investment by the exhibitors and that, when properly used, they are an efficient way of adding to professional knowledge and … Read More → "A Nice DATE in Nice"

Powering Up

They were completely unprepared for what they saw when they stumbled upon it. This was supposed to be wild, untouched back-country. As far as anyone knew, no one lived this far out in the woods. And yet there it was: an old cabin, dilapidated but for the primitive upkeep that kept it intact.

There was only one inhabitant; no one knew who he was. From what they could guess, his parents had died when he was a kid. At the time, he must have been old enough to have learned to talk and scratch … Read More → "Powering Up"

Xilinx Strengthens Its Defenses

Designing for military and aerospace applications can be tough sometimes. The other designers – you know, the ones that do commercial applications – can have the pick of any cool technology they want to use. If some new femtowatt terahertz nanodollar FPGA rolls off the fab line, those commercial designer kids can grab it and go. You, on the other hand, have to stick with only devices that are certified, proven, specially packaged, and … old. It’s like they’re going out on dates in their Dad’s new Porsche or Ferrari while you can either drive your own Citroen deaux … Read More → "Xilinx Strengthens Its Defenses"

Managing More Freedom

It’s all about degrees of freedom. The more of them you have, the more options you have. In the mechanical world, we think of it primarily as the number of dimensions within which you can move: a universal joint can bend in any direction because it has three axes of rotation, one for each of the three spatial dimensions. Three degrees of freedom. When an ant walks on a beach ball, even though it’s a 3-D object, it has only two degrees of freedom because it’s constrained to the surface of the ball. … Read More → "Managing More Freedom"

Cadence Uses the F Word

Mentor brought us Leonardo, Precision, ModelSim, and Catapult. Synopsys sells Synplify and HAPS. Magma brought us Palace and Blast FPGA. Big EDA companies have had anything from a toenail to a whole leg dangling in the FPGA pool for years now… except Cadence.

Like a politician skillfully skirting a controversial issue, Cadence deftly danced around the FPGA domain without touching – one big boot in the IC/ASIC design world, and another firmly planted at the board/system level – with the word “FPGA” never crossing their lips.  When you were designing a board with your Cadence tools, … Read More → "Cadence Uses the F Word"

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