FPGAs end up in the thick of the datapath in most applications today.  Whether the device is bridging between incompatible protocols, blasting bits over a backplane, or performing massively parallel signal processing — in each of these cases, a massive data stream comes into our FPGA, gets munged around by all our wonderful FPGA fabric and internal blocks, and then the result is streamed out of our FPGA on its way to some final destination.  While much of our design focus is what goes on “between the I/Os,” the limiting factor is often the bandwidth of … Read More → "Samplify Supercharges ADC"

1888.  One thousand eight hundred eighty eight.  That’s the number of conference attendees reported in the “Preliminary Attendance Figures” for the 46th Design Automation Conference (DAC) held last week in San Francisco.  The press release proclaims attendance was up “more than 12% over last year.”  

Four years ago, in 2005, in an article titled “Ditchin’ DAC” I gave a brief history of the Design Automation Conference and wove a controversial tiny-tome telling why I thought the conference and the industry it represents were walking … Read More → "Dueling DACs"

Did you hear the story about the fabless semiconductor company that began shipping a family of 10 different devices within months of being founded?

Or the story about the company that developed and shipped a USB 2.0 High Speed device endpoint, supporting multiple audio channels with DSP audio enhancement, in not much more than a couple of months?

Or the company that claims to offer a field programmable device that can be designed in days, programmed in seconds, has a sleep mode of less than 500μW and a selling price of under $5?

No? You … Read More → "Parallel Cores and C"