Courage Under Fire Drill
September 1, 2009
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… Read More → "Courage Under Fire Drill"Power Consumption at 40 and 45nm
August 31, 2009
At 40 and 45 nm process nodes, power has become the primary factor for FPGA selection. This white paper details how Xilinx designed for this new reality in its recently introduced Spartan®-6 (45 nm) … Read More → "Power Consumption at 40 and 45nm"
I/O Design Flexibility with the FPGA Mezzanine Card (FMC)
August 31, 2009
The FPGA’s inherent flexibility has proven indispensable for the creation of external I/O interfaces. However, unless I/O is implemented on a daughter card (mezzanine module), replacing the physical I/O components and connectors requires … Read More → "I/O Design Flexibility with the FPGA Mezzanine Card (FMC)"
Taking Advantage of Advances in FPGA Floating-Point IP
August 31, 2009
Recently available FPGA design tools and IP provide a substantial reduction in computational resources, as well as greatly easing the implementation effort in a floating-point datapath. Moreover, unlike digital signal processors, an FPGA can support a DSP datapath with mixed floating- and fixed-point operations, and achieve performance in excess of 100 GFLOPS. This is an important advantage, for many high-performance DSP applications only require the dynamic-range floating-point arithmetic in a subset of the total signal processing.
… Read More → "Taking Advantage of Advances in FPGA Floating-Point IP"
Catching Mr. X: Diagnosing CDC Errors in FPGAs
August 25, 2009
One of the more popular board games of the 1980’s was Scotland Yard, a game of co-operation in which each player is a detective… except for the shady “Mr. X,” the villain. Over the course of the game, the team of detectives collaboratively chases Mr. X across the city of London. At various points in the game Mr. X appears to the detectives but then just as quickly disappears again. If the “good guys” are able to work together to execute a containment plan, they can catch Mr. X. If not, Mr. X … Read More → "Catching Mr. X: Diagnosing CDC Errors in FPGAs"
Taming a Tenth of a Terabit
August 25, 2009
When the bandwidth glut funnels its way from the bundle of “last-miles” into the big aggregators, switching our packets with ever-increasing density – we inevitably reach the point of the Big Pipe. The Big Pipe is always the limit of our technology – the most bits we can cram into a single cable so we can run them across the floor to another machine.
Every couple of years, the size of the Big Pipe increases – through some clever convolution of Moore’s Law. Today, we sit on the threshold of 100 billion bits per second. In Ethernet. … Read More → "Taming a Tenth of a Terabit"
Fill Solutions Are Getting Smarter
August 25, 2009
As the industry begins production at 45-nm geometries, one of the issues that needs to be resolved is that of planarity—the flatness of the IC after chemical-mechanical planarization. At 45nm and below, fill solutions become much more challenging, because manufacturing processes and physical interactions become more sensitive to small metal density variations.
A big part of the problem is that the allowable thickness variation has remained constant at +/-15%, even while the total thickness of wires has decreased. This dichotomy means that the percentage of total … Read More → "Fill Solutions Are Getting Smarter"
Decisions, Decisions, and Threads
August 25, 2009
The whole way through creating your SoC you are faced with decisions. Some of the hardest decisions, since they are the most difficult to change if they are later seen as sub-optimal, are those made at the architectural level. How do you assign the tasks that you need in order to produce the performance you want, at a reasonable cost in IP licences, silicon real estate, power consumption, and end product performance? For this part of the application, we really require the number crunching of a DSP, while over here we want the flexibility of running an OS, say … Read More → "Decisions, Decisions, and Threads"
Simplifying Processor-Based Designs in FPGAs
August 25, 2009
Using processors in FPGAs? It doesn’t have to be complicated. Join Amelia Dalton as she chats with Steve Wenande of Xilinx about Simplifying Processor-Based Designs in FPGAs.
The webcast discusses the basics of getting a processor-based design up and running in … Read More → "Simplifying Processor-Based Designs in FPGAs"
Unpicking the Codes
August 25, 2009
We did think of “ARM for Dummies” as the title of this guide to the arcane, but ultimately logical, world of ARM architectures and processors, but since none of you are dummies and we were uncertain about the copyright position of “… for Dummies,” we decided not to. Instead here is a simplified map through architectures, implementations, and jargon.
ARM-based chips ship in the millions each week: the ARM website claims that 90 ARM processors are shipped every second! Over 200 semiconductor companies are shipping products with ARM processors in them. (Makes Intel Inside seem … Read More → "Unpicking the Codes"
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