Anthony Torza, Sr. Technical Marketing Manager of Serial Transceivers at Xilinx, demonstrates a Virtex-6 HXT FPGAinteroperating with Finisar 100G form-factor pluggable (CFP) optics.
… Read More → "Virtex-6 HXT FPGA 100G CFP Demonstration"Rob Green, broadcast marketing manager describes how Xilinx has created a new Broadcast Connectivity Kit for our Virtex-6 FPGAs as part of our Targeted Design Platform approach for the broadcast market.
… Read More → "Xilinx Virtex-6 Broadcast Connectivity Kit"Xilinx 7 series FPGAs offer breakthrough power, performance, & dramatically reduced development time.
… Read More → "Xilinx 7 series FPGAs"Learn about using the Altera® high-definition video reference designs to deliver high-quality up, down, and cross conversion (UDX) designs for standard-definition (SD), high-definition (HD), and 3 gigabits per second (Gbps) video streams in interlaced or progressive format. These reference designs are highly software and hardware configurable, enabling rapid system configuration and design. The designs target typical broadcast applications such as switcher, multiviewer, converter, and video conferencing products.
… Read More → "High-Definition Video Reference Design Application Note"As system bandwidths continue to increase, memory technologies have been optimized for higher speeds and performance. The next generation family of Double Data Rate (DDR) SDRAMs is the DDR3 SDRAM. DDR3 SDRAMs offer numerous advantages compared to DDR2. These devices are lower power, they operate at higher speeds, offer higher performance (2x the bandwidth), and come in larger densities. DDR3 devices provide a 30% reduction in power consumption compared to DDR2, primarily due to smaller die sizes and the lower supply voltage (1.5V for DDR3 vs. 1.8V for … Read More → "Implementing High-Speed DDR3 Memory Controllers in a Mid-Range FPGA"
PDN designs targeting transceiver (SERDES) FPGAs require clean voltage sources with strict voltage rail requirements. This document describes the advantages of modern switching voltage regulators in a power distribution network (PDN) design to achieve the best FPGA transceiver performance. This white paper provides guidance on voltage regulator selection for low-noise applications, and a test case that demonstrates the transceiver performance for different types of voltage regulators and voltage rail configurations.
Synopsys and Teradici: ASIC Prototyping Made Fast and Efficient with Synplify Premier.
… Read More → "Teradici Success Story"Now there’s a 100 percent MIPS-compatible soft processor available just for Altera® FPGAs and HardCopy® ASICs. The MP32 is also the industry’s first soft processor that runs the VxWorks operating system.
Watch this 10-minute video to learn five reasons why you should use MP32 in your next custom embedded design. You’ll also see:
Altera’s new device configuration mode – configuration via protocol (CvP) – can be used with PCI Express® to configure the core fabric of Altera’s 28-nm Arria® V, Cyclone® V, and Stratix® V FPGAs. CvP can reduce product cost and board size, while simplifying the software usage model, and providing robust in-field system upgrade capability. In addition, the autonomous, embedded PCIe IP core helps ensure that designs meet PCIe power-up time requirements, irrespective of the FPGA … Read More → "FPGA Configuration via Protocol"
With many advanced applications in the market today requiring high and varying precisions, implementing complex digital signal processing (DSP) can be a challenge. Altera’s innovative variable-precision DSP blocks not only support high-performance signal processing, but also the unique precision requirements of your signal processing designs.
Watch this webcast to find out more about the variable-precision DSP blocks in our 28-nm Arria®Read More → "Enabling High-Performance DSP with Arria V or Cyclone V Variable-Precision DSP Block"
