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Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC

Nearly all new ASIC and SOC designs incorporating digital audio employ some form of programmable DSP to run the audio codecs.  General-purpose control processors can implement audio codecs with a sufficiently fast clock. However, they are not the most efficient engines for running audio codecs, and almost always use more energy to deliver real-time, multi-channel audio.

DSPs generally run audio codecs more efficiently than do general-purpose processors because they have features that accelerate the … Read More → "Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC"

Cut DSP Development Time – Get High Performance From C, No Assembly Required

DSP software developers have traditionally converted key performance-critical portions of their algorithms to assembly language because that was considered the only way to achieve high performance when using a DSP core. Every DSP architecture is different – optimized for a different type of data throughput challenge – and programmers need to understand each underlying DSP architecture in order to optimize the code manually using assembly coding techniques.  Thus specialized knowledge is required to achieve effective results.

Read More → "Cut DSP Development Time – Get High Performance From C, No Assembly Required"

Get Your ASICs and SoCs Off the Bus!

The choice of hardware-interconnection mechanisms among processor blocks in an SOC affects communication performance and silicon cost. The default on-chip communications choice for most ASIC and SOC design teams is the global bus or a bus hierarchy, however this choice automatically incurs many performance and design problems.

There are other choices that may be more appropriate for today’s nanometer ASIC and SOC designs. These choices match well with communications concepts frequently used by … Read More → "Get Your ASICs and SoCs Off the Bus!"

Next Generation System Validation Using Transactors

Emulation: The Enabler for Hardware-Software Co-Verification

Using an emulator for ASIC verification holds the promise of extremely high execution speed, enabling the validation of system-level scenarios that are unthinkable with simulation farms. With MHz speeds, today’s fast emulators can crunch enough cycles to run entire software application stacks on top of an SOC and truly perform hardware software co-verification. However, having a fast and accurate model of the ASIC solves only half of the problem. … Read More → "Next Generation System Validation Using Transactors"

Reducing Power Consumption and Increasing Bandwidth on 28nm FPGAs

Lower power consumption and higher bandwidth are now the two dominant requirements in designing next-generation high-end applications. The global trend across multiple markets is for higher bandwidth in the same footprint at the same or lower power and cost. The Internet is going mobile and video is driving bandwidth requirements at a growth rate of 50% year on year. The march to 40G and 100G systems (with 400G on the horizon) is underway to support this ever-growing bandwidth demand. Fierce competition is driving down prices. Space constraints abound, and … Read More → "Reducing Power Consumption and Increasing Bandwidth on 28nm FPGAs"

Maximizing the Power of ARM with DSP

Texas Instruments’ (TI) Integra™ DSP+ARM devices combine a digital signal processor (DSP) and an ARM® processor, enabling developers to create applications best suited for executing a combination of signal processing tasks and microprocessor (MPU) tasks. This paper reviews the benefits of combining ARM processing with DSP processing in a single chip, including increased real-time performance, improved system flexibility and reduced system cost and power. Integra DSP+ARM processors are useful for applications such as power protection systems, industrial control, machine vision and … Read More → "Maximizing the Power of ARM with DSP"

C2000™ MCU Motor Control Primer

There is a significant demand for well-equipped digital motor control (DMC) platforms to educate the next generation of engineers.  In this users guide, a number of introductory-level digital motor control methodologies and laboratory tools are presented. These tools help engineers learn how to easily construct their own systems using TI provided device drivers, APIs, utilities, and libraries. Also learn about TI’s motor control developer’s kits, software framework, and DMC library. These documents provide a modular development strategy which allows the user to experiment incrementally from a basic … Read More → "C2000™ MCU Motor Control Primer"

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May 16, 2025
Whatever the age into which you were born, if you were a kid enjoying something, the odds were that it was corrupting your soul....