I’m still chafing under the impositions imposed by the punctuation police. I speak of those who don the undergarments of authority and stride the corridors of power. Those despicable despots who dictate I can no longer terminate the titles to my columns with exclamation marks, all the time muttering inscrutable incantations to their SEO gods. Fortunately, I’m not bitter.
Talking about punctuation (did you see what I just did there?), I was just chatting with Dirk Seynhaeve, who is VP of Business Development at Sigasi (or S;gas; as they stylize themselves in their logo). As we will see, this stylization derives from their “Put your sem;colons to work ;” tagline.
Putting one’s semicolons to work (Source: Sigasi)
Since the folks at Sigasi are relatively (some may say “almost completely”) unknown in the Americas and the Asia-Pacific region, it’s tempting to say they are emerging from stealth mode. On the other hand, this would be a tad misleading, since the company has been “hiding in plain sight” in Europe since its founding in 2008. That’s 16 years ago as I pen these words, which equates to multiple lifetimes in Electronic Design Automation (EDA) space (where no one can hear you scream).
There’s a lot of ground to cover here, but I’m going to attempt to boil things down for the sake of all our sanities. Sigasi was founded by two students at the University of Ghent in Belgium who were working with the hardware description languages (HDLs) that hardware design engineers use to capture their FPGA and ASIC designs. These students—Hendrik Eeckhaut Ph.D and Philippe Faes Ph.D—were disgruntled with the EDA tools from different companies because each tool expected and employed a different file organization structure and pulled everything (the multiple files forming a design) together in different ways.
They decided to take something the software world had been doing for countless yonks (that’s a lot of yonks), which was to use an Integrated Development Environment (IDE) that—apart from anything else—imposes structure onto your myriad source files and libraries and whatnot.
At that time, they created their IDE (called Sigasi Studio) using Eclipse, which was the most popular platform at that time. Also, they focused their attentions on VHDL, which was the primary HDL used in Europe. In turn, this led to them becoming huge in European FPGA design. As a result, they now have thousands of enthusiastic customers in Europe while managing to remain “a riddle wrapped in a mystery inside an enigma,” to the rest of the world, as Winston Churchill might have said.
As an aside and to set the scene—in the same way C++ may be regarded as being a superset of C (this isn’t strictly true in a mathematical sense, but it’s “close enough for government work,” as they say), so may SystemVerilog be considered as being a superset of Verilog.
It’s probably fair to say that one’s choice of HDL is dependent on both region and application/industry. It’s also not unfair to say that VHDL tends to be more used in Europe as a region, and in military and space applications in general, while SystemVerilog tends to find favor in America as a region, and in commercial applications in general. But times change. Eclipse is no longer the IDE of choice, and SystemVerilog and VHDL can be found all over the place (both industry-wise and geographically speaking)—often coexisting in the same companies, establishments, and organizations (see also Language Wars in the 21st Century: Verilog versus VHDL—Revisited).
To address these trends and to address the needs of a worldwide market, Sigasi recently announced its Sigasi Visual HDL (SVH) portfolio, which is capable of handling designs represented in SystemVerilog and/or VHDL for ASIC, ASSP, SoC, and FPGA devices that will end up containing hundreds of billions of transistors. Furthermore, this latest incarnation of the tools is fully integrated with Microsoft’s Visual Studio Code (VS Code), which is currently the most popular IDE on the planet.
My understanding is that 80% of software developers already use VS Code as their IDE of choice, so having hardware design engineers work with the same IDE cannot help but be advantageous when it comes to hardware-software co-design, integration, validation, and verification.
Who amongst our number doesn’t love three-letter acronyms (TLAs)? Bearing this in mind, a screenshot of the SVH IDE GUI is shown below.
The SVH IDE GUI (Source: Sigasi)
“So, what’s the big deal—isn’t this just another IDE?” I hear you muttering under your breath. Well, let me expound, explicate, and elucidate (don’t worry, I’m a professional). It’s not the IDE per se—it’s the tools under the IDE hood.
Let’s start with the fact that pretty much every statement in an HDL ends with a semicolon. The folks at Sigasi say that they put these semicolons to work (actually, they put every character in your code to work, but it sounds catchier when they spotlight the semicolons).
SVH validates your HDL code. It makes sure that your code makes sense syntactically, that it makes sense semantically, that it adheres to corporate coding styles, that it takes care of function safety, that it’s aware of vulnerability issues, that… the list goes on.
“But don’t other tools do this?” you say. Well yes, but those tools tend to be targeting completed code that is poised for use by other tools like simulation and synthesis engines. As a result, they tend to run once on a full-up version of the design (or a fully defined subset). By comparison, SVH verifies your complete code constantly (every 200 milliseconds or so).
Note that, by “complete.” I mean “everything you give it” and not necessarily “the complete design.” Sigasi’s secret sauce is that SVH can look at a whole bunch of files, even if the collection doesn’t represent a complete design and/or even if each file isn’t itself complete. Furthermore, it can do all this while you’re in the process of writing your code.
For example, you can type something, and the tool will tell you, “You’re employing an obsolete way of using UVM here—you can fix this by…” If you accept the suggested fix, the modification will be applied. Or say you’re creating a state machine (in which case you can see a graphical view as you enter code in the textual view) and you include a default state even though you’ve already covered all possible situations, this will be flagged in real-time, and so it goes. When you’re ready to rock and roll, SVH can feed the design to the simulation and/or synthesis engines of your choice, including addressing any dependency trees (different compilers have different orders they prefer to see things in), creating UVM sequences and topologies, and so on and so forth.
There’s so much more to tell but so little time to tell it all in. Your best bet is to take SVH for a spin by Installing VS Code (assuming you don’t already have it installed), then using the VS Code interface to look for Sigasi, and then installing the free Community (non-commercial) Edition of SVH. If you do give this a whirl (or if you are already a devotee), I’d love to hear any thoughts you’d care to share.
Visual Studio and C# are really great for Logic Design and Debug! Not at all like the pitiful VHDL and Verilog
That start with synthesis and timing driven placement. HDL is hardware DESCRIPTION language.
C# has conditional assignments instead of load/compare/branch/assign nonsense and the equivalent of HLS that actually works. No wonder, C# was created by an engineer! (and a team of excellent programmers)
And I forgot to mention that expression evaluation is stack based rather than being dependent on a weak kneed RISC and C compiler.
Hi Karl — although C (and eventually C++) are great for describing, simulating, and verifying things at a high-level of abstraction — back in the day there was no way to take these descriptions into a gate-level implementation other than by hand. It’s worth noting that C/C++ compilers don;t go direct to machine code, instead they go to an intermediate assembly language representation (which is what people were creating by hand before C/C++ compilers came along), which is subsequently assembled into machine code “under the hood.” It’s great that we now have high-level synthesis (HLS) that can take C/C++ as a staring point, but the output is an intermediate representation in the form, of HDL.
I remember when the first HDLs came on the scene. I worked with GenRad HDL (GHDL) which in many respects was the precursor to Verilog (Phil Morby worked GHDL before he created Verilog). Having a language that could represent the concurrency of hardware (where multiple things can be happening at the same time) was awesome.
I cannot believ tha someone familiar wsith the
Boy! I mangled that!
I cannot believe that some one familiar with the TTL Data Book could write that. Right up front they say the limits are whatever they are capable OR WANT
Boy! I mangled that!
I cannot believe that some one familiar with the TTL Data Book could write that. Right up front they say the limits are whatever they are capable OR WANT
So. here goes:
1) There is no way to increase performance meaningfully using edge triggered flip-flops. Clock frequency, skew, and heat dissipation are the prime factors. Exceptions include functional blocks, including block memories. Note that true dual port memories are key, but the separate read and write clocks are more tolerant to clock skew.
2) Simple polarity hold flops “hold” the data while it is clocked/set into the next stage.
3) The designer can focus on “what it does” and not “how long does it take”
4) I first used this methodology in 1964 when IBM was developing SLT technology for System360.
5) It worked out of the box and for other designs as well.
Oh, yes Electronic Design Automation — Automated Logic Diagrams and Printed Circuit Boards were part of the mix. (Yes, Max the designer had to specify logic function, physical location, pin assignment, etc)
Hi Karl — I’m not sure what point you are trying to make — you say that there’s no way to increase performance meaningfully using edge-triggered flip-flops. OK, but what does that have to do with this column? I don’t mention performance anywhere.
All I said was: “SVH validates your HDL code. It makes sure that your code makes sense syntactically, that it makes sense semantically, that it adheres to corporate coding styles, that it takes care of function safety, that it’s aware of vulnerability issues, that… the list goes on.”
Sorry, Max.
All I said was: “SVH validates your HDL code. It makes sure that your code makes sense syntactically, that it makes sense semantically, that it adheres to corporate coding styles, that it takes care of function safety, that it’s aware of vulnerability issues, that… the list goes on.”
And that leaves me no choice but to use HDL . I am OK with that, sort of. Just that I cannot comprehend how in he world do I describe hardware that has not been designed?
Seems there’s a missing link. Let me dub it LDL and to point out that VS VSCODE fully supports conditional assignments, events, delegates, lambda functions, etc.
So, let us get the ole yeller book out and define C# classes with the same inputs, outputs, functionality.
Now the challenge is to define 2 registers, assign arbitrary values and assign the and, or, exclusive or
values to 3 other variables. note that variable names begin with a l;etter and numerics are values and that the compiler will determine the type for the var name.
Now the hard part press start. Oh, yes you can set a break point and hover over the name to see the value.
No, I was trying to point out that Verilog may be reaching end of life for other reasons. Farewell.
I find that sad — I was there at Verilog’s beginning — I can’t believe that I might live to see its end 🙁