It was recently SPIE Advanced Litho time again, and… well, the belle of the ball appears to be changing. For several years, now, it’s been “all EUV all the time.” OK, there’s always lots of other stuff going on, but everyone (including your intrepid reporter) breathlessly awaited the latest EUV details.

EUV a Done Deal?

Well, EUV is kind of old news now. Yeah, there’s lots of work ongoing to bring further improvements, but, to address the big issue of the past, “Source power is no longer an issue,” as stated by ASML’s Michael Lercel. At 250 W (which isn’t a new data point), it’s enabled the shipments of 18 ASML EUV systems last year, with 30 more expected this year. Their improved 3400C unit should ship at the end of the year, bringing throughput to 170 wafers per hour. They expect the first EUV-enabled chips to hit the market by the end of the year.

So are we done with EUV? Well, not quite. Amongst other ongoing details (resists, pellicles, etc.), a high-NA version (NA of 0.55), as we’ve mentioned before, is under development – but it’s a couple of years out. Whereas, last year, anamorphic lenses were the subject of several papers, this year it’s all about annular lenses – circular lenses with a dot in the middle that blocks 0^th-order light for better contrast.

That aside… what else happened at the conference?

Well, two common themes (that sometimes intersect) were edge-placement error (EPE) and stochastics. The first takes what used to be called simply “overlay” and builds a more holistic picture of all of the effects that can be a challenge when trying to align features (or aspects of features) atop each other. The second deals with the frustrating randomness that contributes to issues like line-width roughness.

It’s not like there were specific sessions devoted to these issues; it was rather that, within many sessions, papers addressed one or another aspect of one or both of those topics. We should expect to hear more if any of the many factors gets a head of steam as a major improvement.

So, then, was there anything else interesting?

Scanning Probes

In fact, there was. In the quest for making nanometer-scaled features, there were several papers on scanning-probe microscopy (SPM) and lithography (SPL). No, those aren’t ways by which aliens view our activities from above or brand our skin with their planet’s logo. It’s a way to create very small patterns – by some descriptions in a manner that’s too slow for high-volume production. But, as we’ll see, another paper proposed a way to scale up throughput.

First, let’s review SPL and some of the variants. All of them involve a very fine probe at the end of a cantilever. This is what’s used for atomic-force microscopy (AFM). Exactly how the probe interacts with the surface below, and what it accomplishes, are what separate the variants.

First, there’s field-emission SPL (FE-SPL). This works by emitting electrons from the tip of the probe across an air gap to the surface, consistent with Fowler-Nordheim transport. The energy lies in a range that can expose resist, making it useful for lithography. No vacuum is needed. Because of the extremely localized source of electrons, proximity effects are greatly reduced, since you don’t have secondary electrons running amok and blurring features, as can happen with standard e-beam lithography.

Second, there’s thermal SPL (tSPL). This uses a current that concentrates at the probe tip to make it hot, melting resist. Because it literally removes the resist, this is a self-developing process, meaning that a separate development step after “exposure” isn’t needed. There were also papers discussing tSPL as used for creating protein gradients or magnetizing miniscule domains, but that’s not what I’m going to focus on today.

Then there’s SSPM: sub-surface probe microscopy. For this, the probe is used as a microscope that can see even as far as microns into the lower surface, including through metal-based resists. This can be useful for ensuring correct placement of fine features – like a fine contact hole over a fine line somewhere underneath the surface.

There’s also a companion challenge to patterning resist with ultra-small features: transferring that pattern down into the underlying layer(s), which requires extreme anisotropy. One paper discussed cRIE: cryogenic reactive-ion etching. In principle, this sounds very similar to Deep RIE (DRIE) in passivating sidewalls to prevent sideways etching. But the details are different. By using oxygen and fluorine in the plasma, you get SiOxFy, which is volatile at normal temperatures. But, at low temperatures (hence the “cryogenic”), it sticks to the surfaces and passivates them. Sputtering then removes the horizontal passivation layer at the bottom of the feature for further etching, sparing the sides with occasional low-energy glancing blows.

With this background, then, what was achieved in the two papers that I focused on?

A broad-ranging team from the Ilmenau University of Technology (Germany), Nano Analytik GmbH (Germany), Imperial College London (UK), Turkish National Research Institute of Electronics and Cryptology (Turkey), Koç University (Turkey), and TU Ilmenau (Germany) used FE-SPL and cRIE to create functional single-electron transistors. The effective minimum feature size was 1.8 nm.

They were able to use the probe both in SPL and in AFM modes, allowing for pre-exposure inspection, alignment, exposure, and post-exposure inspection using the same probe. Because the process is inherently slow, they see this as appropriate for creating prototypes or for patterning nano-imprint lithography (NIL) blanks.

The second paper, from a team at TNO in Delft, the Netherlands, also used the probes three ways – and additionally proposed a way to achieve throughput high enough for commercial manufacturing. In this case, they created very small holes through metal-oxide resist, again using the probe for pre-exposure alignment and post-exposure inspection. While they discussed tSPL, in the end, they used simple mechanical force to punch a hole in the resist. Which would also be self-developing.

The average hole diameter was around 22 nm; the range was from 20ish to 25ish nm (based on histograms they showed of area and circumference). The pitch between holes ranged, in their experiment, from 100 down to 25 nm (intentionally; that’s not an indication of huge variation).

Using the word “exposure” is a bit of a stretch for both of these papers. At least, in the first paper, the resist was “exposed” to electrons. In the second paper, there’s no exposure to anything except brute force. As to transferring the hole in the resist down into the underlying layer, the second paper provided no details. In fact, it’s entirely possible that they didn’t take that extra step, focusing only on the resist. I didn’t get a specific response to my question on that; if I get one after the fact, I’ll update.

As to the second paper’s idea for doing this faster in production? Simple: parallelism. That’s frankly how e-beam lithography is being scaled. In this case, it’s not multiple columns of electron beams; it’s multiple probes. They don’t appear to have implemented such a system (rather non-trivial), but they put it forth as a scaling mechanism.

More info:

Ivo W. Rangelow et al, “Field-emission scanning probe lithography with self-actuating and self-sensing cantilevers for devices with single digit nanometer dimensions,” Proc. SPIE 10584, Novel Patterning Technologies 2018, 1058406 (19 March 2018); doi: 10.1117/12.2299955

Violeta Navarro et al, “High-throughput scanning probe instruments for nanopatterning, alignment, and overlay metrology,” Proc. SPIE 10584, Novel Patterning Technologies 2018, 1058404 (19 March 2018); doi: 10.1117/12.2294994