While Altera and AMD continue to hammer away at the higher end of the FPGA spectrum – for example, see “AMD ups the ante in the RF-enabled FPGA poker game with the Versal RF family” – Lattice Semiconductor’s recent introduction of the Nexus 2 FPGA platform reconfirms the company’s commitment to smaller FPGA devices. Although the Nexus 2 platform employs a fairly advanced 16nm process node, FPGAs based on Lattice’s Nexus 2 platform will have fewer than 200K logic cells, which is relatively small these days. Instead of going for all-out performance and large programmable logic fabrics, Lattice is using the benefits of TSMC’s 16nm FinFET process node to emphasize specific capabilities such as faster boot time and lower operating power.
Lattice’s original Nexus platform, introduced in 2019, was based on Samsung’s 28nm FD-SOI process. Its higher-end Avant platform, announced in 2022, is also based on TSMC’s 16nm FinFET process. Presumably, the Nexus 2 platform leverages the same or a similar version of the 16nm TSMC process and benefits from the lessons that Lattice undoubtedly learned about making FPGAs with this process node over the past two years. At introduction, Lattice announced that it planned to use the Avant platform to make FPGAs with as many as 500K programmable logic elements, while the Nexus 2 platform will be used for significantly smaller devices.
The table below illustrates several of the performance benefits that Lattice realizes with the 16nm Nexus 2 platform when compared against the original 28nm Nexus platform.
Lattice’s 16nm Nexus 2 FPGA platform delivers significant benefits over the company’s original 28nm Nexus platform, including more system logic cells, more and faster SerDes ports, a faster EEPROM interface, more DSPs, faster and PCIe. Image credit: Lattice Semiconductor
Relative to the original Nexus platform, the Nexus 2 platform supports more than twice as many on-chip system logic cells, improves SerDes data rates, boosts the maximum clock rate from 200 to 350 MHz, more than triples the number of on-chip DSP blocks, bumps PCIe speeds from Gen 3 to Gen 4, and more than doubles bandwidth between the FPGA and external SDRAM. System designers using FPGAs should find all these improvements to be significant.
According to Lattice, these improvements deliver the following benefits:
- Much faster boot times using external Flash EEPROM configuration memory.
- Significantly lower power consumption
- Smaller form factors for packaged devices
- A simplified power delivery network that eliminates the need for power supply sequencing
- Enhanced data security using popular (but not post-quantum) cryptographic algorithms (AES-CGM, SHA-3, ECDSA, and RSA)
During a demo for Tirias Research Principal Analyst Francis Sideco, Lattice Semi’s Senior Director of Product Marketing Deepak Boppana demonstrated the advantages of the Certus-N2 CT20 FPGA, the first of the company’s devices to be based on the Nexus 2 platform, against an Altera Cyclone 10 GX 220 FPGA and an AMD Artix UltraScale+ AU20P FPGA. All three devices were mounted on the same circuit board, and all three ran the same FPGA configuration, which consumed approximately 107K logic cells and which was stored in a single external boot ROM for each FPGA.
During the demo, each FPGA asserted an external signal pin to signal completion of the configuration phase. The Lattice Certus-N2 CT20 FPGA completed its bootup from EEPROM in 18 msec, while the Altera Cyclone 10 GX 220 FPGA and AMD Artix UltraScale+ AU20P FPGAs booted in 361 and 261 msec respectively. According to the company’s white paper, this part of the demonstration shows that the Certus-N2 CT20 boots as much as “20 times faster than the competition.”
Lattice attributes this faster boot time to several factors. First, the Certus-N2 FPGA employed a 160 MHz clock for the interface to its external EEPROM, which was much faster than the AMD AU20P FPGA’s 127.5 MHz and nearly three times faster than the Cyclone 10GX220 FPGA’s 60 MHz. Note that the Cyclone 10GX FPGA family has grown fairly long in the tooth. Altera, when it was Intel, announced these devices in early 2017, nearly eight years ago. Cyclone 10 GX FPGAs are manufactured using a 20nm planar FET process and therefore do not employ FinFETs, which exhibit less static current leakage than do planar FETs.
The AMD Artix UltraScale+ devices are somewhat newer, having been introduced in early 2021 when the devices were still marketed under the Xilinx banner. That was before AMD bought Xilinx. Artix UltraScale+ devices are manufactured using TSMC’s 16nm FinFET+ process node, which is therefore similar or identical to the process node used to manufacture Lattice’s Certus-N2 FPGAs.
Lattice’s comparison of its latest devices against competitors’ devices that are years older is a favorite trope for semiconductor companies. Oranges and apples. Would I expect a brand-new FPGA family to outperform competitors introduced four to eight years ago? I’d be sorely disappointed if they did not outperform their much older competition. Such is the world of semiconductors.
The second factor affecting boot time is the QSPI interface implementation. The AMD and Altera FPGAs used in this demo employed a 4-bit-wide QSPI Flash interface running at Single Data Rate (SDR) speeds while Lattice’s Certus-N2 FPGA supports the 8-bit DDR xSPI Flash interface with four times more bandwidth when running at the same clock rate. However, as noted above, Lattice’s Certus-N2 FPGA also employs a faster clock rate for the QSPI interface. Of course, the Certus-N2 device boots faster!
Finally, Lattice claims that the Nexus 2 FPGA platform’s use of 4-input LUTs reduces the number of required configuration bits relative to AMD’s 6-input LUTs and Altera’s 8-input LUTs, which further reduces boot times. (Note that all three FPGAs have about the same number of on-chip logic cells.) In fairness, Lattice admits that 6-input LUTs can deliver better performance because they might be able to implement more complex functions with fewer logic stages.
In the same White Paper, Lattice compares the power consumption of the three FPGAs using the same configuration file. Unsurprisingly, Lattice again wins this competition. (It’s not surprising because Lattice wrote the White Paper.) The Certus-N2 FPGA requires significantly less operating power at all clock frequencies from zero to 300 MHz.
Lattice attributes this result to one significant factor: the Certus-N2 FPGA’s 4-input LUTs draw less static and dynamic power than AMD’s 6-input LUTs or Altera’s 8-input LUTs. Lattice also notes that 4-input LUTs consume less real estate than the larger LUTs, but this argument essentially restates the claim of lower static power in a different way because chip area strongly correlates with static power consumption.
It’s possible that the Artix UltraScale+ FPGA might have run faster than the Certus-N2 FPGA device for the demo configuration. We don’t know, because the demo didn’t push the clock rate past 300 MHz. The maximum clock rates for these two devices will vary according to the configuration, so if you want to benchmark the speed performance of these two FPGAs against each other, you’ll need to dump your compiled HDL code into both of them to see which device wins.
Perhaps of even more interest to system designers is the fact that Certus-N2 FPGAs do not require power supply sequencing. One of the biggest headaches in designing FPGA-based systems is getting the power sequencing right so that the FPGA doesn’t blow up while powering on or off – or worse, doesn’t blow up under corner-case conditions. This Certus-N2 feature truly delivers value with this feature alone.
Lattice’s website currently shows four members in the Certus-N2 family, ranging from the CT07 with 65K system logic cells, 120 18×18-bit DSP blocks, and four 16Gbps SerDes ports to the CT20 discussed above with 220K system logic cells, 520 18×18-bit DSP blocks, and eight 16Gbps SerDes ports.
Lattice’s Nexus 2 Platform White Paper ends with an interesting statement:
“Future Nexus 2 families will introduce additional features, including integrated flash memory, enhanced security, faster D-PHY and hardened C-PHY capabilities, further solidifying Lattice’s position as a leader in low power small FPGAs.”
We eagerly await news of the next FPGA family to be based on the Lattice Nexus 2 platform. Meanwhile, samples of and evaluation boards loaded with Certus-N2 FPGAs are available now.
References
Lattice Semiconductor White Paper, “Lattice Nexus 2 Platform: Low Power, High Performance Small FPGA,” 2024
Steven Leibson, “Lattice Strides Into the Mid-Range FPGA Arena With Avant,” EEJournal, December 21, 2022
Tirias Research, “Lattice Semi Dev Con 2024 – Nexus 2 Getting AI to the Edge using Small FPGAs,” December 16, 2024
