I just got off a video conference call with a company I cannot name that’s developed a technology I cannot discuss to power a product I am forbidden to talk about at this time. But I fear I’ve said too much. Suffice it to say that this product is going to enable a new generation of high-performance computing (HPC) and artificial intelligence (AI) platforms in data centers.
But that’s not what I wanted to talk about, so I’ll say no more.
Of course, saying “I’ll say no more” reminds me of a classic scene from the 1987 American romantic comedy movie, Moonstruck, starring Cher as a widowed Italian American woman called Loretta Castorini. Loretta falls in love with her fiancé’s hot-tempered, estranged younger brother, Ronny Cammareri, who is played by Nicolas Cage. The scene in question takes place between Loretta’s father, Cosmo, and her fiancé, Johnny:
Cosmo: You’ll have your eyes opened for you, my friend.
Johnny: I have my eyes open.
Cosmo: Oh yeah? Well, stick around. Don’t go on any long trips.
Johnny: I don’t know what you mean.
Cosmo: I know you don’t. That’s the point. I’ll say no more.
Johnny: You haven’t said anything!
Cosmo: And that’s all I’m saying.
The timing and presentation were impeccable. I’m still laughing. Moonstruck is an awesome movie. Now I want to watch it again, but we digress…
I’m currently reading a science fiction novel called Agency by American-Canadian author William Gibson. This book is described as being both a sequel and a prequel to William’s previous novel, The Peripheral, which has rapidly risen to the top of my “wish list” of books for Christmas.
Agency has two plots that are intertwined. One is set in an alternative version of 2017, with a young woman named Verity testing a new form of avatar software called Eunice that was developed by the military. The second plot line involves people in a post-apocalyptic 22nd century meddling with what’s happening in 2017. And then things start to get confusing.
Eunice is an advanced AI, who is initially presented to Verity as a sophisticated digital assistant. However, Eunice turns out to be far more capable, self-aware, and strategic than her creators anticipated.
“Well, this is all very interesting,” I hear you muttering under your breath, “but what on Earth does this have to do with the ‘GenAI-Powered Design and Verification EDA Tools’ that were promised in the title to this column?” I’m glad you asked. I’m poised to expound, explicate, and elucidate. I just dispatched the butler to retrieve my orating trousers. He’s not as young as he used to be, so we’ll have to give him a moment…
… that’s better. Now we’re ready to rock and roll (fortunately, these are multi-function trousers).
As I’ve mentioned before, when I started my career, my first position on leaving college was as a member of a team designing central processing units (CPUs) for mainframe computers. This was at International Computers Limited (ICL) at their West Gorton facility in Manchester, England. One of the best things about this job was that each junior engineer, like yours truly, was assigned to an older, more experienced mentor. I was extremely fortunate to have Dave Potts as my mentor. He made me into the man I am today (so please feel free to address any complaints to him).
These days, I often receive plaintive emails from young engineers who have just started their own first jobs and have been dropped into the deep end with no one to whom they can turn to for support and to ask questions.
Although they’ve been in the public domain for less than two years as I pen these words, Generative AI (GenAI) systems like ChatGPT have taken the public consciousness by storm. Even my 94-year-old mother is au fait with the concept of GenAI, for goodness’ sake (I just wish she’d stop asking me so many hard-to-answer questions).
GenAI is already helping software developers. For example, I believe that GitHub Copilot now generates about 60% of embedded application source code in programming languages like C, C++, C#, Java, Rust, etc. Also, the GenAI that calls itself Metabob can help in identifying bugs and security weaknesses in one’s code.
In the case of hardware designers, tools like Flux.ai’s Copilot provide a promising option for the creators of printed circuit board (PCB)-level designs (see my column, May the Flux (Copilot) Be with You!). But what about the folks designing and verifying silicon chips in the form of ASICs, ASSP, SoCs, FPGAs, and SoC FPGAs? Are there any GenAI platforms out there for them?
Well, by golly, I’m happy to say: “Yes, there are!” Earlier today, I enjoyed a wide-ranging video chat with representatives from three companies who are bringing GenAI capabilities into Electronic Design Automation (EDA) space (where no one can hear you scream). The idea is to help the guys and gals designing and verifying today’s high-end devices. The way this was described to me was that it’s like having a trusted older engineer standing behind you looking over your shoulder. You can ask questions like… well, just about anything, really, and these AIs will guide you in your task.
The folks in question were Kartik Hegde, who is CEO and Co-Founder at ChipStack, Ann Wu, who is CEO and Co-Founder at Silimate, and Pierre-Emmanuel Gaillardon, who is Chief Strategy Officer and Co-Founder at PrimisAI (he’s also a Professor in the ECE Department at the University of Utah).
Between them, these companies—in the form of their GenAI tools—span the gamut, starting with early-stage concept and architecture discussions, and then progressing through design, layout, verification, and implementation.
Lest I forget, one more member of our illustrious gathering was Rick Carlson, who is Vice President at Verific. This is important because Verific plays a key role with respect to these GenAI tools. So much so, in fact, that I was tempted to title this column Verific is Terrific for GenAI-Powered Design and Verification EDA Tools (but then… I didn’t… I’m sorry Rick).
Verific is an industry stalwart when it comes to the pre-processing, parsing, analyzing, synthesizing, and elaboration of SystemVerilog, VHDL, and UPF. Verific’s software is used worldwide in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, design-for-test, and… now… GenAI applications, because all the aforementioned GenAI companies have selected Verific as their frontend parser.
Verific is terrific (Source: Terrific Verific)
Returning to the topic at hand, what sort of AI-assistance are we talking about here? To be honest, my mind is still reeling from everything I heard. This could be as simple as asking the AI, “How do I create a state machine that does X-Y-Z?” to the AI looking at an existing state machine and telling you, “You don’t need this default case because you’ve already covered all of the bases.”
Now, you may be thinking that this isn’t too amazing, but this is the very simplest level. What we are talking about here is the ability to complement design and verification teams by combining the human-mimicking creative behavior of AI with the deterministic behavior of EDA. We’re talking about tools that can look at your design and create a verification plan (and associated code… and associated documentation) for you.
We’re also talking about GenAI assistants that can read 1000-page+ specifications and data books in seconds to extract information that’s applicable to what you are trying to do. Earlier this year, for example, in my Understanding and Optimizing SoC Hardware Performance column, I talked about the fact that the intellectual property (IP) blocks forming a modern silicon chip—processors, accelerators, DDR memory controllers, Network-on-Chip (NoC) interconnect—are extremely configurable. As I said in that column:
A disturbingly common scenario is for a team of SoC developers to pick processor IP in the form of Arm or RISC-V clusters, to pick DDR IP in the form of a Cadence DDR controller, to create their “secret sauce” IP(s), to select their interconnect IP of choice, to integrate all these IPs together, to perform functional verification, to fabricate the device, and to… watch in abject horror as their baby “crashes and burns” by failing to perform as expected. It’s not unknown for an SoC to achieve as little as 50% of its anticipated data bandwidths. There is much gnashing of teeth and rending of garb on those days, let me tell you. This is where the finger-pointing starts, with the developers accusing the IP providers of offering false promises, and the IP providers standing firm that their IPs perform as pledged. So, who is to blame? What has gone wrong?
In many cases, the problem lies with the fact that each IP has thousands of configuration parameters. These parameters need to be set in such a way as to optimally address the requirements of the anticipated software workloads. Just to add to the excitement and fun, modifying the configuration of one IP can negatively impact the performance of another IP in unanticipated and “interesting” ways.
Now imagine having a troupe of trusted mentors standing behind you—or a gaggle of GenAI mentors working alongside you—who already understand all this stuff. Even better, someone or something that can read and understand everything available with respect to these configuration options and the interactions between them, alert you to any potential problems, and guide you to successful resolutions. Pretty powerful, eh?
Does this mean you have to discard all your existing EDA tools—the curated collection you currently own from EDA giants like Cadence, Mentor (now Siemens EDA), and Synopsys? “No!” I cry, “1,000 times no!” The great news is that, unlike Marc Antony who famously said, “I come to bury Caesar, not to praise him,” these new GenAI tools come to augment the capabilities of existing tools, not to supplant them.
As always, my head is spinning with everything I’ve just heard and learned. It’s going to take me quite some time to wrap my brain around all of this. Sadly, I fear that I’ve failed to adequately describe the power and capabilities offered by the tools from ChipStack, Silimate, and PrimisAI. Happily, Kartik, Ann, and Pierre invite you to reach out to them via their company websites—they will be delighted to explain all the bits I left out (and correct all the parts I put in). What say you? Do you have any thoughts you’d care to share on anything you’ve read here?
