I’m thinking of a RISC-V IP vendor. One that has a 30% market share of the global RISC-V IP market. One whose IP cores are to be found in more than 16 billion system-on-chip (SoC) devices. Are you thinking who I’m thinking?
No, not them, silly! I’m talking about Andes Technology. Since Andes was founded in Taiwan (it’s a public company on the Taiwanese stock exchange), it’s less well known in North America than some of the other guys.
Having said this, I also think it’s fair to note that Andes is known by those who don the undergarments of authority and stride the corridors of power—the folks who demand the highest-performance and most configurable RISC-V processor cores available on the market—not least that around 30% of the company’s revenues come from the US.
Personally, I don’t think it will be long before Andes is at the forefront of everyone’s minds when the conversation turns to matters of a RISC-V nature. In fact, I flatter myself that after perusing and pondering this column, if you ever find yourself chatting with someone who says something like, I’m thinking of a RISC-V IP vendor. One that has a 30% market share of the RISC-V IP market. One whose IP cores are to be found in more than 16 billion system-on-chip (SoC) devices. Are you thinking who I’m thinking? You will immediately respond, “Of course I’m thinking what you’re thinking—it’s Andes, of course!”
The reason I’m now so well informed is that I was just chatting with Marc Evans (Director of Business Development & Marketing) and Darren Jones (Distinguished Engineer & Solution Architect) at Andes.
As you may recall, my first position after university was as a member of a team designing CPUs for mainframe computers. So, you can only imagine my delight to discover that Darren’s personal history is as a CPU designer. He came up in the MIPS era designing 32-bit and 64-bit multi-threaded processor cores, and then moved into designing and building large SoCs. The “Solution Architect” portion of Darren’s title reflects the fact that he now leverages his skills as a CPU designer and an SoC designer to help customers choose the right RISC-V configuration for their own SoC projects.
Even better, Marc also has a history in processor design going back to IBM mainframes and x86 microprocessors. Also, Marc spent many years with IP processor cores at Tensilica (which was acquired by Cadence Design Systems in 2013), whose main claim to fame was its Xtensa configurable processor cores.
As you can imagine, Marc, Darren, and your humble narrator spent a happy time wandering down memory lane (proving that nostalgia is indeed still what it used to be) before proceeding to the topic at hand, which was to bring me up to speed with all the cool RISC-V stuff that’s happening at Andes.
Before we plunge into the fray with gusto and abandon (and aplomb, of course), let’s first briefly remind ourselves that, circa 2010, the processor cores used to power chips like microcontrollers, ASICs, ASSPs, and SoCs were predominantly provided by companies like ARM and MIPS, along with x86 cores from Intel and AMD. Although these processors were (and still are) great, they do have disadvantages, including licensing costs and restrictions, coupled with limited flexibility with respect to customization.
It was around 2010 that the RISC-V (pronounced “risk-five”) project began at UC Berkeley’s Parallel Computing Laboratory (Par Lab). This project was led by Professors Krste Asanović and David Patterson, with graduate students Yunsup Lee and Andrew Waterman. Their goal was to create an instruction set architecture (ISA) that was open and free from licensing restrictions.
Growth was slow at first. In fact, it wasn’t until around 2015 that the RISC-V Foundation was established, at which point things really started to take off. In 2019, the RISC-V Foundation relocated to Switzerland, eventually evolving into the RISC-V International nonprofit business association.
The great thing about RISC-V is that it’s an open standard, meaning anyone can design, manufacture, and sell processors based on the RISC-V specification without royalties or license fees. As a result, the RISC-V ecosystem is exploding, as are shipments of RISC-V-based products. According to global analyst Omdia, RISC-V-based processor shipments are projected to increase by nearly 50% annually between now and 2030, accounting for close to a quarter of the global market by 2030 (that’s not too shabby for a university project).
Now, let’s return to Andes and its RISC-V offerings. Let’s start with the fact that they have north of 500+ employees, most of whom work in research and development. In addition to its R&D team in Taiwan, Andes has spent the past few years building up design teams in the US—in Oregon, Texas, and Washington. In fact, their next-generation ultra-high-performance processor IP is being fully designed in the USA, which I think is very cool indeed.
I also think it’s cool that, since Andes is the only publicly traded RISC-V IP company, it’s really the only one that provides true visibility into the number of IPs it sells, which is why market analysts and companies like the SHD Group like them because it’s always nice to be able to work with numbers you can trust.
It’s also worth noting that Andes was both a founding member and a premier member of the RISC-V Foundation circa 2015, becoming chairs and co-chairs of many of the task groups. In fact, the folks at Andes contributed the DSP extension to RISC-V, and they’ve also contributed many other packages in terms of trusted execution environments and simulation. Today, in addition to being a premier member of RISC-V International, Andes is also a founding member and premier member of the RISC-V Software Ecosystem (RISE) project, whose mission it is to accelerate the development of open source software for the RISC-V architecture.
There are currently 30+ AndesCore RISC-V CPU IP cores available “off the shelf,” as it were. These range from 32-bit small MCUs with 3-stage pipelines, through 32b/64b dual-issue workhorse processors with 5-stage and 8-stage pipelines, to 64b quad-issue out-of-order (OoO) high-performance processors with 12-stage pipelines.
AndesCore RISC-V families (Source: Andes)
The naming convention takes a bit of wrapping your brain around. If there’s a first letter, it’s either N or D or A. The D means that you have a SIMD DSP. The A means it’s an application processor, which means you have both a SIMD DSP and an MMU. If you don’t have A or D, then it’s an N, which means you don’t have A or D (“In order to understand recursion, you must first understand recursion”). Meanwhile, an SE suffix means “Safety Enhanced” (i.e., functional safety ISO-certified).
Where the folks at Andes really start to differentiate themselves is that, in addition to world-leading scalar processor implementations, they also field state-of-the-art vector processing capabilities. Vector processing is key for high-end artificial intelligence (AI) applications, Andes is dominating in RISC-V vector processing space (where no one can hear you scream), and a large part of this domination comes from their being the first to market with RISC-V vectors.
Also, in addition to all the usual data types, including FP8, FP16, and FP32, AndesCore 40-Series vector processors also natively support BF16, which has the same exponent range as FP32 while offering more than 2X acceleration and using only 1/2 the memory for the parameters. This is why BF16 is used extensively by Google, Meta, and Nvidia for both training and inference.
Speaking of which, two examples of AI companies using RISC-V technology from Andes include Meta and RAIN AI (which is backed by Sam Altman, who is CEO of OpenAI).
I fear I’m waffling too much, but before we get to the point of this column (yes, of course there’s a point), I did want to note that another key value proposition the guys and gals at Andes bring to the market is the fact that they support the addition of custom instructions. More importantly, they provide tools that allow their customers to easily and robustly add custom instructions themselves.
I was amazed to discover that around 75% of Andes’ users make use of this custom instruction capability. Although Andes also offers this as a service, most customers want to do it themselves because they see it as being part of the “Secret Sauce” that will differentiate their SoC(s) from competitive offerings. This involves the use of Andes Automated Custom Extension (ACE), which features an automated tool called Copilot that does all the heavy lifting.
Andes ACE and Copilot (Source: Andes)
ACE and Copilot support both scalar and vector processor implementations. In addition to adding custom instructions to the RISC-V IP itself, Copilot also extends the tools to support these instructions, including the compiler, assembler/disassembler, debugger, integrated development environment (IDE), instruction set simulator (ISS), and so forth.
The aforementioned RAIN AI, which was funded by Sam Altman, makes use of both vector processing and custom instructions in their AI SoCs. In fact, they presented a very interesting talk on this topic at last year’s RISC-V Con 2024.
All of which leads us to the fact that RISC-V Con 2025 is almost upon us. This auspicious (and FREE) event—which brings together industry leaders, innovators, and developers in the RISC-V ecosystem—will take place on Tuesday the 29th of April 2025 in San Jose. There will be two tracks running in parallel: (1) The Main Conference and Exhibits and (2) a Developer Track.
The Developer Track features four 1-hour sessions designed for engineers who want to take a deep dive into RISC-V technology:
- Optimization with RISC-V Vector ISA: Curious about RISC-V Vectors (RVV) but unsure how it works? This session covers the basics and how it boosts vector performance. You will get hands-on experience writing and running vector software using AndeSight tools on RVV-capable processors.
- IAR Professional Tools for RISC-V: Learn how professional tools can help you debug your application more quickly and efficiently, accelerating your time to market. Also, discover how prequalified Functional Safety tools can enhance your products.
- Create Your Own RISC-V Custom Instructions: Want to create your own RISC-V Instructions to accelerate your application? This session explores Andes’ Automated Custom Extensions (ACE) for enhancing the RISC-V ISA, with a hands-on demo using Andes Copilot, which automates much of the process.
- Optimizing SoC Performance with Baya’s WeaverPro Software: Building a complex SoC with high memory demands? Avoid surprises! See how WeaverPro software analyzes CPU/GPU traces to uncover bottlenecks, validate enhancements, and optimize performance. A deep-dive demo will show you how to collect data, run simulations, and refine your design.
Remember that RISC-V Con 2025 is FREE. The Main Conference and Exhibits are open to all attendees. By comparison, I’m informed that seating is limited for the Developer Track, so be sure to select this option when registering! Also, attendees of the Developer Track are advised to bring their laptops fully charged!
I have so much more I wish to say about the RISC-V IP cores and tools from Andes, but I fear that this will have to wait for another day. Until then, do you have any thoughts you’d care to share on anything you’ve read here?
