AMD has made another play in the poker game for RF-capable FPGAs against Altera. AMD’s opening ante, actually Xilinx’s opening ante, was the introduction in early 2017 of the first RFSoC, based on the existing Zynq UltraScale+ SoC. Altera’s counter, in late 2022 back when Altera was still Intel, was to introduce the Agilex 9 Direct-RF series of FPGAs. The two companies have taken different manufacturing approaches to making these RF-enabled FPGAs.
AMD took the monolithic route, which fabricates high-speed analog converters on the same die as the FPGA fabric. Conversely, Altera employs Intel’s EMIB (embedded multi-die interconnect bridge) packaging technology to couple high-speed analog converter die to the main FPGA die within the FPGA’s package. As a result of being able to integrate the fastest available analog converters in the form of chiplets, Altera’s RF-enabled FPGA attains the stratospheric ADC sample rate of 64 Gsamples/sec with 10-bit resolution. (Note: Since the introduction of the Agilex 9 Direct-RF SoC FPGAs, Intel has added the AGRM027 to the Direct-RF FPGA family with 14-bit ADCs with a slower sample rate of 12 Gsamples/sec.)
As a result of choosing the monolithic route, the AMD RFSoC’s maximum sample rate had been limited to 6 Gsamples/sec for the device’s fastest speed grade. AMD has now upped its ante in the poker game with the introduction of its Versal RF line of RF-enabled FPGAs, which have as many as eight 14-bit ADCs capable of reaching 32Gsamples/sec conversion rates. (Note: AMD prefers to refer to its Versal devices as ACAPs – Adaptive Compute Acceleration Platforms – and Adaptive SoCs, for the devices that incorporate hardened processing systems. As far as I can tell, no one outside of AMD uses this uniquifying nomenclature. A rose by any other name…)
Based on the specs of these competing devices, you can infer that Altera and AMD are targeting different markets in the RF arena. Altera had previously stated that its target market for the Agilex 9 Direct-RF FPGA family was military/aerospace equipment including radar, SIGINT (signal intelligence), and EW (electronic warfare) systems.
AMD is also targeting specific applications in the military/aerospace realm with the RFSoC – specifically applications such as phased-array radar, military communications, and EMSO (electromagnetic spectrum operations), which include EW (electronic warfare), spectrum management, CEMA (cyber electromagnetic activities), and SIGINT. In addition, AMD is targeting satellite communications and test and measurement applications with its Versal RF FPGA family. Test and measurement applications include high-speed DSOs (digital sampling oscilloscopes), wideband spectrum analyzers, and high-speed RF ATE (automatic test equipment). These additional target applications will exploit the higher resolution of the Versal RF FPGA’s ADCs and potentially lower device cost, thanks to the Versal RF FPGA’s monolithic construction.
The figure below shows a Versal RF chip layout and calls out the most significant resources on the FPGA.
AMD Versal RF chip layout and significant resources. Image credit: AMD
Because Versal RF FPGAs are designed for direct-RF applications, the devices’ ADCs and DACs can easily be considered the most significant resources on the chip. The Versal RF FPGA’s analog converters are based on three tile types, as shown in the image below.
AMD Versal RF FPGA’s three high-speed ADC tiles. Image credit: AMD
Two of these tiles consist of four integrated ADCs and four integrated DACs respectively. One of these quad tiles contains four 8Gsamples/sec RF-ADCs, and the other contains four 16Gsamples/sec RF-DACs. The final tile contains one RF-ADC capable of 32Gsamples/sec conversion rates. The RF-ADC tiles incorporate hardened channelizers, which break the conversion stream into lower-rate channels and hardened decrementers. The RF DAC tiles incorporate hardened channelizers and hardened incrementers. The hardened decrementers and incrementers support DDC (digital down conversion) and DUC (digital up conversion) operations. The RF-ADCs also support programmable decimation (periodic sampling) by as much as 80x.
The table below shows how many of each type of analog converter you get in each of the four planned Versal RF FPGAs.
The four members of the AMD Versal RF family incorporate different numbers of ADCs. Image credit: AMD
If your application needs the fastest ADCs available in the Versal RF device family, then you can get four or eight of the 32Gsamples/sec ADCs in one device. If your application doesn’t require the maximum available ADC conversion rate, you can get sixteen 8Gsamples/sec ADCs in one VR1952 FPGA. These Versal RF FPGAs also incorporate eight or sixteen 16Gsamples/sec DACs. Simply put, that’s a lot of analog RF converters in one package, which should be especially attractive for phased-array radar and test and measurement applications that require many analog converter channels.
With all of this RF conversion capability generating heaps of data, Versal RF FPGAs need to bring substantial processing power to bear on the resulting data streams. To do this, the Versal RF FPGAs inherit many of the existing processing elements in AMD’s line of Versal FPGAs, including programmable AI engines, DSP blocks within the Versal device’s FPGA fabric, and a hardened processing system, which integrates a dual-core Arm Cortex-A72 application processor and a dual-core Arm Cortex-R5F real-time processor.
The combined processing resources in Versal RF FPGAs can throw as much as 80 TOPS of computational power against any high-performance signal-processing problem. Of course, that 80-TOPS number is a theoretical maximum. It would be impossible to harness all of the Versal RF processing elements smoothly into one large conglomerate processor, just as it’s impossible to harness horses, oxen, and elephants into an effective team for pulling one wagon.
Versal RF FPGAs also incorporate multiple hardened processing blocks that add application-specific computational capability. These hardened blocks include an FFT/inverse-FFT block, an LDPC decoder, and a polyphase arbitrary resampler. It’s possible to build these functions using the Versal RF FPGA’s programmable logic fabric, but putting these functions into hardened blocks reduces the operating power relative to designs that would implement these functions in the FPGA fabric and reserves the resources in the FPGA fabric for truly unique functions.
With all that computation, Versal RF FPGAs need a hefty chunk of memory bandwidth to move raw data into and computed results out of the FPGA. This hefty bandwidth is supplied by DDR5/LPDDR5 memory controllers that support transfer rates of 6400 MTransfers/sec for DDR5 SDRAM and 8533 MTransfers/sec for LPDDR5X SDRAM. The result is a maximum of 136.5 Gbytes/sec of peak external memory bandwidth on the largest Versal RF devices. The Versal RF FPGAs’ memory controllers incorporate optional hardened encryption and decryption blocks that operate at speed.
AMD plans to publish a White Paper that further describes the Versal RF FPGAs and their applications by the end of January. Check the company’s website to see if it’s available. Versal RF device samples are scheduled to be available towards the end of 2025, but production silicon won’t be available until 2027.
Between the AMD and Altera RF-enabled FPGA families, you should be able to find at least one device to meet your high-speed RF conversion needs. If not, you’ll need to wait to see what happens in the next round of this high-end RF-FPGA poker game.
Resources
Kevin Morris, “Radio FPGA! Xilinx Announces RFSoCs,” EEJournal, February 21, 2017.
Steven Leibson, “Intel Takes Control of Communications Hill with Analog-Enabled FPGA Portfolio,” EEJournal, October 3, 2022.
Steven Leibson, “Why does Xilinx say That its New 7nm Versal ‘ACAP’ isn’t an FPGA?,” EEJournal, October 11, 2018.
