AMD has announced the eventual appearance of 2^nd-Generation Versal Premium FPGAs. Plans for this new generation include four devices with 643,456 to 1.5 million LUTs and 3332 to 7616 DSP blocks. Most of the logic fabric inside these 2^nd-generation devices remains architecturally unchanged from the first generation, but there’s been an emphasis on more DSPs and relatively fewer LUTs. This architectural change targets mil/aero, test and measurement, and 6G comms applications. The new Versal FPGA generation will be built on TSMCs 6nm process (N6), a shrink of the 7nm process (N7) used to manufacture the original Versal FPGA generation. You can expect to see these devices more than a year from now, with samples appearing in the first half of 2026, so you have plenty of time to think about how you might use such a high-end programmable logic device in your future designs.

AMD’s Versal Premium Gen 2 FPGA family currently includes four devices. Image credit: AMD

Architecturally, the 2^nd-generation Versal Premium devices look a lot like the first generation. The programmable logic fabric incorporating the LUTs and the DSPs is unchanged, although the mix for the two types of internal fabric blocks has been jiggered for the target applications. Also unchanged is the hard processor subsystem, consisting of dual-core Arm Cortex-A72 and dual-core Arm Cortex-R5F processor cores. So, what’s changed? There’s been a lot of under-the-hood tinkering with the Versal Premium FPGA’s portfolio of peripherals to tailor the parts more closely to the target applications.

Let’s start with the memory controllers and interfaces. Versal Premium Gen 2 devices will support LPDDR5X SDRAM running at 8533 MTransfers/sec and DDR5 SDRAM running at 6400 MTransfers/sec with as many as eight internal SDRAM controllers. These local memory speeds represent double the transfer rates compared to Versal Premium Gen 1 devices, which supported the previous generation LPDDR4 and DDR4 SDRAM. These speeds also approach the memory speeds previously made possible by HBM memory stacks available in some Versal Premium Gen 1 devices, but at lower cost and with larger memory capacities. In addition, the Versal Premium Gen 2 internal SDRAM controllers will support ECC, encryption, and the CXL 3.1 specification, which permits memory expansion, sharing, pooling, and tiering for large multi-processor arrays such as those found in data centers. These enhancements help the FPGA to access more memory, faster, which is an essential characteristic for FPGAs tasked with processing large amounts of data as fast as possible.

However, processing data faster is only part of the task at hand. That data needs to be fed into the FPGA’s domain from a host or some input subsystem, and the processed data needs to be extracted from the FPGA’s domain. Both the input and output latencies need to be as small as possible to maximize system throughput. Consequently, AMD appears to have spent the bulk of its effort on improving the Versal Premium Gen 2 devices’ memory and system interfaces.

The Versal Premium Gen 2 devices’ high-speed SerDes transceivers have been revamped so that one transceiver design supports serial data rates of 1.25 Gbps to 128 Gbps and NRZ or PAM4 encoding. First generation Versal Premium devices needed two different transceiver designs to cover this range. As a result, developers using the first generation Versal Premium devices needed to understand the details and idiosyncrasies of two different SerDes transceivers, and AMD’s device designers needed to divine the ideal mix for the two transceivers when envisioning the first-generation devices. Versal Premium Gen 2 devices incorporate only the new GTM2 SerDes transceivers, although some of the transceivers in some of the Gen 2 devices will be throttled due to package lead-length and device power limitations. The four Versal Premium Gen 2 FPGAs incorporate 32, 56, or 72 of these transceivers. One application that will need the 128 Gbps capabilities of these transceivers is test and measurement, where PCIe Gen7 testers will need the maximum bit rates of the new transceivers.

Versal Premium Gen 2 devices’ support of PCIe Gen6 builds upon the improved GTM2 SerDes transceiver design with two PCIe controllers that can support two 8-lane PCIe Gen6 host interfaces, which run at 64 Gbps per lane. The PCIe Gen6 controllers also support hardened inline ECC and data encryption to protect data in flight at line rates and the CXL 3.1 protocol to support advanced multiprocessor memory sharing and pooling in large systems. In total, the Versal Premium Gen 2 FPGA’s support of local DDR5/LPDDR5 SDRAM and CXL memory expansion creates an aggregated external memory bandwidth of more than 500 Gbytes/sec.

For some reason, AMD decided that it was a good idea to reuse an existing high-speed crypto engine in the Versal Premium Gen 2 devices. This engine is not a post-quantum engine. The Versal Premium Gen 2 crypto engine supports today’s crypto standards such as AES, MACsec, and IPsec. Putting these soon-to-be obsolete functions into a device that won’t be in production until mid-2026 seems shortsighted to me, but some applications may need it. When I asked about the omission of post-quantum crypto support, the reply I received was “there’s always the programmable logic.” <Insert sound of me grinding my teeth, see “NIST Issues New Quantum Crypto Standards for Cyberspace.”>

AMD incorporated additional I/O capability into the Versal Premium Gen 2 devices for specific applications. A new hardened LDPC (low-density parity check) block adds capabilities to encode data streams for noisy environments. This feature targets some very specific applications including 6G RANs (radio area networks) and satellite communications. A high-speed MIPI interface block that supports the C-PHY and D-PHY protocols specifically targets sensor and display test equipment designs. (It’s very hard for me to envision using a high-performance Versal Premium Gen 2 FPGA in conventional MIPI applications such as security cameras.)

Given that CXL has yet to penetrate data centers or any other memory-intensive applications, it’s a good thing that the Versal Premium Gen 2 devices won’t arrive for more than a year. During that year, it’s possible that hyperscaler and other data center architects may more fully embrace the CXL concepts of memory sharing, tiering, and pooling. Wider adoption awaits suitable applications that would justify the added cost of CXL memory. According to data presented by AMD during the Versal Premium Gen 2 unveiling, nearly half of the installed based of data center servers are CXL-capable today, and the expectation is that virtually all servers will be CXL capable by 2027. However, that same data indicates that essentially none of these servers are exercising their CXL capabilities in 2024, and fewer than ten percent of these servers are expected to be using their CXL capabilities by 2027. Whatever the CXL adoption rate turns out to be, it will likely be driven by server CPU considerations, not by FPGAs. (For more discussion about CXL, see “The Adventures of CXL Across the 3rd Dimension.”)

Although not an enhancement to the silicon, AMD is packaging at least some of the Versal Premium Gen 2 devices in a compact 35x35mm form factor, which is good for mil/aero applications that use the 160×100 mm VPX-3U board form factor and for test and measurement applications, where space and lead lengths inside of high-speed testers always represent significant design challenges.

All in all, AMD’s Versal Premium Gen 2 FPGAs appear to be an educated tweak or a makeover of the original Versal Premium family rather than a full generational upgrade. AMD seems to have learned quite a bit from initial discussions with customers and has refreshed the Versal Premium product line accordingly.