At the recent Embedded World held in Nuremberg, Altera made an announcement and wants you to know two things: Agilex 3 FPGAs are now in production, and you can order them now. Altera also announced development support for Agilex 3 FPGAs (along with Agilex 5 E-series FPGAs and MAX10 programmable logic devices) through a no-cost Quartus license, and development boards from iWave and Terasic. The company will continue to offer its Cyclone V FPGAs, which will be less expensive than Agilex 3 FPGAs with similar numbers of logic elements (LEs). During a preview of the Embedded World announcement, Altera CEO Sandra Rivera explained that the expense difference was due to the Agilex 3 devices having nearly twice the fabric performance compared to their Cyclone V counterparts (“up to 1.9x”) with reduced power consumption by as much as 38 percent, and because Agilex 3 devices include a hard processor system (HPS) based on an 800Mhz, dual-core, 64-bit Arm Cortex-A55 processor. Even clocked at 800MHz, a pair of Arm Cortex-A55 processors can handle a lot of conventional processing tasks.

I have reported on Intel’s and Altera’s slow rollout of Agilex 3 FPGAs in previous articles. (See “The First Annual FPGA Awards – the Fibbies – celebrating 40 years of FPGAs” from January, 2025, “Altera unveils slightly more detail about the Agilex 3 FPGA family a year after announcing it” from November 2024, and “Intel Heats Up and Expands its Agilex FPGA family” from October 2023.) These years-long FPGA rollouts remind me of Salome’s Dance of the Seven Veils.)

To refresh your memory, in that article from last November, I wrote:

“… the Agilex 3 FPGA family would include devices with 25K to 135K logic elements, which squarely overlays the company’s aging Cyclone V FPGA family. The Agilex 3 family will therefore usher end-product designs in the Cyclone V FPGA class into the Agilex architectural tent.”

The article then continued:

“…the low-end Agilex 3 FPGA family and the mid-range Agilex 5 FPGA family overlap quite a bit with respect to logic element count. However, there’s a significant difference in the amount of on-chip memory, the number of multipliers, PCIe support (PCIe 3.0 versus PCIe 4.0), SDRAM support, I/O count, and high-speed serial transceiver count between the Agilex 3 and Agilex 5 FPGA families. The Agilex 3 parts have fewer of these resources, and that’s precisely what you’d expect from a differentiated low-end product.”

These observations remain accurate; however, I gleaned additional details about the Agilex 3 device family during Rivera’s Embedded World preview. First, the FPGA fabric in Agilex 3 devices incorporates the latest, most advanced iteration of Altera’s DSP block, which has been augmented for AI applications by melding the floating-point DSP support from early Agilex devices with tensor math features inherited from the company’s Stratix 10 NX FPGA. Only the latest Agilex families incorporate these AI Tensor blocks. Second, Agilex 3 FPGAs incorporate the Agilex Secure Device Manager (SDM), a dedicated, triple-redundant processor that serves as a sentry and security guard for all JTAG and configuration commands.

A sub-minimalist block diagram of an Agilex 3 FPGA shows the Hard Processor System (HPS), the Secure Device Manager (SDM), PCIe 3.0 x4 and 10 GbE Ethernet controllers, and an LPDDR4 memory controller, all surrounding 25K to 135K programmable logic elements (LEs). Image credit: Altera

During her preview of the Embedded World announcement, Rivera said that Altera was specifically targeting four application categories with Agilex 3 devices:

1. The Data Center – applications include a platform root of trust and board management.
2. Smart Factories – applications include sensor fusion, motor control, and functional safety.
3. Autonomous vehicles (including cars, UAVs, and drones) – applications include object detection and collision avoidance.
4. Medical – applications include vision processing and diagnostic imaging for endoscopes and MRI scanners.

Of course, you can use these FPGAs for a wider range of applications. They’re general-purpose FPGAs.

As of press time, iWave was already showing an SOM based on the Agilex 3 FPGA on its Web site. From the specifications, it appears that the SOM is available with more than one member of the Agilex 3 FPGA family. The SOM’s features include:

• Agilex 3 C-Series FPGA in an M16A Package
• Dual-core Arm Cortex-A55 Processor, clocking at up to 800MHz
• As many as 135,110 Logic Elements
• 4 Gbytes of LPDDR4 SDRAM for the HPS (expandable to 8 Gbytes)
• 32 Gbytes of eMMC Flash memory (expandable to 128 Gbytes)
• 1 Gbyte of QSPI Flash memory (expandable up to 2 Gbytes)
• Four high-speed serial GTS transceivers operating as fast as 12.5Gbps
• 2.5G Ethernet PHY Transceiver
• USB 2.0
• 10+ Years long-term support

The iWave Agilex 3 SOM accommodates multiple members of Altera’s Agilex 3 FPGA family. Image credit: iWave.

Earlier this year, I wrote an article about Lattice Semiconductor’s new Nexus 2 platform. (See “Lattice Semiconductor’s Nexus 2 platform brings significant performance benefits to low-end FPGAs.”) If you refer to that article, you’ll see that Lattice’s original Nexus platform included FPGAs with 21K to 130K “system logic cells” (an entirely made-up number based on a magic gearing ratio between system logic cells and LEs), and that the Nexus 2 platform includes FPGAs with 65K to 220K system logic cells. In Lattice’s case, one system logic cell is considered more than two LUTs. In Altera’s case, one logic element consists of a LUT and a register, and in AMD/Xilinx’s case, the math is slightly more complex due to the definition of a “logic cell” involving 4-input LUT equivalents.

Without stepping any further into the tar pit of old arguments about LEs, logic cells, and system logic cells, it’s clear that Altera’s Agilex 3 FPGA family challenges Lattice’s low-end FPGAs. As far as relative capacities are concerned, the only way to make a firm determination is to take your design and fit it into competing FPGAs using the supplied design tools. It’s a royal pain to do that, considering the many niggling differences in source code requirements for tools from various manufacturers, not to mention the different design flows, but it’s the only way to know for sure.

Currently, Lattice offers one device family based on the Nexus 2 platform: the Certus-N2 FPGA family, although more FPGA families based on the Nexus 2 platform are sure to be in the pipeline. One obvious advantage that Agilex 3 FPGAs have over Lattice’s Certus-N2 FPGA family is the Altera dual-core HPS. The Agilex 3 family incorporates an HPS, and Lattice’s Certus-N2 family does not. Considering that nearly every system designed today makes good use of software-programmable microprocessor cores, having an on-chip HPS is likely to be a real advantage for nearly every design.

Also, Agilex 3 FPGAs’ 12.5 Gbps SerDes transceivers are slightly faster than the 10.3 Gbps SerDes transceivers in Certus-N2 FPGAs, although you can get eight high-speed transceivers in at least one Certus-NX FPGA, while the maximum number of SerDes transceivers available in Agilex 3 devices is four. Both FPGA families support PCIe Gen 3.0 x4 and 10 GbE Ethernet with hard IP.

When Intel first announced the Agilex brand on April 2, 2019, the name represented the company’s high-end FPGA brand. At the time, Intel claimed that the Agilex FPGA family delivered 40 percent more performance than the existing Stratix 10 FPGA family while consuming 40 percent less power. It should never be a surprise and always go without saying that a new FPGA generation is faster than the previous generation and that it consumes less power. If the new generation was more power-hungry and slower, now that would be a surprise. There’d be no reason to ever introduce an FPGA generation like that.

Over time, Intel has pushed the Agilex brand lower into the FPGA hierarchy, first into the mid-range Agilex 5 families and now into the low-end Agilex 3 families. Having one FPGA architecture that covers the full FPGA range is a real advantage. Altera is a year reborn since its newly declared independence from Intel, and the company continues to spread the Agilex brand and architecture throughout its device portfolio with. It’s exciting to see Altera and AMD/Xilinx devoting renewed attention to the low end of the FPGA market. For years, these two FPGA leaders left the low end to Lattice, Microchip, and relative newcomer Efinix. Finally, FPGA developers are getting what they want: some real competition at the low end.