By the time you read this article, you should be able to get Adiuvo Engineering’s new Leonidas Spartan 7 Tile. It went on sale for pre-order in August for £150.00. Unlike FPGA development boards, Adiuvo’s Leonidas Spartan 7 Tile is designed to be used as a component in a larger design. The 59x59mm tile is a circuit board with a periphery of castellated interconnect pads that will take 0.1-inch headers or will just solder down onto a larger PCB without the headers.

Adiuvo Engineering designed its Leonidas Spartan 7 Tile to be used as a component in your own design, making it easy to integrate an AMD/Xilinx Spartan 7 FPGA into your board. Image credit: Adiuvo Engineering

The Leonardo FPGA Tile incorporates a relatively small AMD/Xilinx Spartan 7 XC7S25 FPGA with 23,360 logic cells, 80 DSP blocks, and 45 BRAMs. The Tile also incorporates 256Mbits of QSPI EEPROM for configuration memory and 32Mbits of external SRAM. The Tile has 82 I/O connections, including power, ground, and JTAG pins along with 32 3v3 I/O pins and 41 I/O pins that have configurable I/O voltages. The reason for sourcing an FPGA in board (or Tile) form is to accelerate early prototype development by acquiring the FPGA in a format that permits hand wiring. The FPGA itself is packaged in a ball grid array (BGA).

One aspect of the Tile that’s not obvious from the specification: the board also handles all the supply voltages required by the FPGA. The board runs from a single 4.5V to 18V power supply and manages all the voltages required by the FPGA and the other on-board devices. This is a design detail that you need not bother with when using the Tile rather than developing your own chip-level, FPGA-based design.

Adiuvo Engineering is owned by Adam Taylor, who wrote the MicroZed Chronicles published online by Xilinx for many years and now available here. He’s a successful design engineer specializing in space-centric FPGA applications, but he’s got broader embedded experience and knows how to fit FPGAs into a variety of earthbound applications. He’s also the co-author of a book titled “A Hands-On Guide to Designing Embedded Systems,” which introduces readers to the design of FPGA-based systems. The book discusses techniques and principles that need to be considered before starting an FPGA-based project and provides an overview of the engineering life cycle when developing an electronic solution from concept to completion.

A while back, Taylor published a White Paper titled “Migrating Spartan 6 Design to 7 Series & Beyond WP02 – FPGA Design Considerations.” I wrote an article about this White Paper titled “Spartan-6 vs Spartan-7: Should I Stay or Should I Go?  Adam Taylor Helps You Decide Whether to Migrate from Xilinx Spartan-6 to Spartan-7 FPGAs,” back in early 2022, but you should really get the White Paper if this topic interests you.

Xilinx announced the Spartan-6 FPGA family in 2009. The Spartan FPGA families are the company’s low-cost leaders – AMD/Xilinx would prefer that I say “cost-effective” instead – and the Spartan-6 FPGA family is based on an aging 45nm IC process technology that’s increasingly hard to source as the supply chain for 45nm devices continues to dry up. Xilinx was slow to upgrade the highly successful Spartan-6 FPGA family and dragged its heels for years. Finally, the company announced the 28nm Spartan-7 FPGA family in 2015. This FPGA family is likely to be around for a while because the 28nm process node remains the most cost-effective node in the semiconductor industry’s node menagerie. AMD bought Xilinx in 2022 and announced the latest member of the Spartan FPGA family, the Spartan UltraScale+ FPGA family based on TSMC’s 16nm FinFET process node, in March 2024. However, the Spartan-7 FPGAs are likely to be the low-cost leaders for many more years.

Adiuvo envisions a range of applications for the Leonidas Spartan 7 Tile including:

• Power supply sequencing
• Power monitoring
• Configuration management
• Board management/supervision/communications
• Protocol conversion
• Sensor fusion/aggregation
• I/O expansion
• Processing offload
• System health and usage monitoring systems
• Rapid prototyping

Of course, the board incorporates an FPGA, so the application space for this product is truly large.

Perhaps the biggest change between Spartan-6 and Spartan-7 FPGA families is the upgraded tool chain used for development and implementation. Spartan-6 devices required the use of Xilinx’s older ISE, EDK, PlanAhead, and SDK tool chain. The Spartan-7 Series devices use the much newer Vivado and Vitis tool chains. As Taylor writes in his White Paper:

“Vivado is a quantum leap in capability compared to the older ISE tool chain. Vivado enables developers to work with pure RTL designs and leverage a large inbuilt IP Library using IP integrator. IP Integrator is ideal for creating embedded system designs which contain processors within either the processing system of a heterogeneous System on Chip or softcore implemented in logic such as MicroBlaze.”

AMD now offers a configurable version of the MicroBlaze soft processor based on the RISC-V ISA. It’s called MicroBlazeV, which supports both 32- and 64-bit versions of the core and optionally supports the following RISC-V ISA extensions:

• Multiplication and division (“M” extension)
• Atomic instructions (“A” extension)
• Floating-point (“F” extension)
• Code compression (“C” extension)
• Bit manipulation (“Zba”, “Zbb”, “Zbc”, “Zbs” extensions)

Different configurations of the MicroBlaze V processor range from a low of 625 LUTs for a minimum-sized, 32-bit processor core to 9366 LUTs and 14 BRAMs for a 64-bit, “frequency optimized” MicroBlaze V core. Taylor used a MicroBlaze V processor core to help ring out the Leonidas Spartan 7 Tile.

Taylor named the new product the Leonidas Spartan 7 Tile because he considers the Spartan-7 family to be the king of the Spartan families. As he is the author of several hundred MicroZed Chronicles blogs, you might expect the Tile to have above-average documentation, and your expectations would be correct. The Tile’s documentation includes:

• A user guide
• A schematic
• A Vivado Board definition
• Reference designs including IP to enable processor access to FPGA internals using the UART or SPI ports
• A Tile footprint in Altium to help accelerate your circuit board design

In addition, you can hire Adiuvo Engineering to either develop a complete application based on the Tile or to assist you with developing your application.