The first six parts of this article series described developments at major semiconductor vendors that played big roles in the MOSFET’s development. However, because fabs were relatively easy to create in the early days of ICs, there are many smaller stories as well. The following story, about one HP division’s involvement in MOSFET and NMOS development, happens to be one of those smaller stories that I’m personally familiar with, which is why it’s the seventh and final article in this brief history of the MOS transistor.
Loveland, Colorado was a tiny agricultural and retirement community in the 1960s. Sugar beet fields surrounded the town and the Great Western Sugar Company’s White Satin sugar plant stood between Interstate 25 and the town’s core. If ever there was a list of unlikely places to find a global center of MOSFET development, Loveland would have been a top-ten choice.
Despite the low likelihood, Loveland became the site for the first Hewlett-Packard manufacturing plant to be built outside of California. Dave Packard was born in Colorado, so that’s where HP sent Stan Selby to look for a suitable plant site. He first stopped in Boulder, home to both the University of Colorado at Boulder and the US National Bureau of Standards (now called the National Institute of Standards and Technology or NIST). The university promised to be a potential source of new HP engineering recruits and NBS was a potential customer and development partner.
Paul Rice and Bob Hipps of Loveland knew that new industry would be needed to revitalize their sleepy farming town. Rice was president of the Loveland First National Bank, and Hipps was a local appliance dealer. The two men had started the Loveland Development Fund to acquire land for an industrial site. Rice and Hipps learned that an HP representative was scouting for a plant site nearby. After checking out the company’s reputation, the two Loveland businessmen contacted Selby and invited him to make the half-hour drive north from Boulder to see the town. Apparently, they were convincing, because HP selected Loveland as the location for its Colorado manufacturing plant and had it operating by 1960.
HP opened the Loveland plant to manufacture power supplies, voltmeters, and audio-video instruments that had been designed in California. HP’s research and product development were still centralized in Palo Alto in 1960. Shortly after the Loveland plant opened, HP started to decentralize its product development. HP’s Loveland Division started its own R&D lab inside a Quonset hut in 1961, and Marco Negrete moved to Colorado from Palo Alto to become the HP Loveland Division’s first engineering manager.
Over time, HP Loveland assumed responsibility for the development of HP’s voltmeters, signal generators, and several other types of instruments. Negrete realized that HP Loveland needed a truly unique product to call its own if it was to thrive, and when HP Labs developed a prototype desktop scientific calculator in 1966, Negrete managed to stake his claim and pull responsibility for productizing and manufacturing the new product into Loveland’s sphere.
The HP 9100A desktop calculator became a huge success when it was introduced in early 1968, and HP Loveland suddenly found itself in the business of designing and manufacturing advanced desktop computing equipment. By the end of the year, the HP 9100A had become one of HP’s top four revenue-producing products, averaging 200 units per month. Within a year, the new desktop calculator business was as large as HP’s 211X minicomputer business. (Note: Many people confuse HP’s desktop calculators with its more famous handheld calculators. They’re not the same and came from different HP divisions.)
The HP 9100A desktop calculator had a 64-bit, microprogrammed, VLIW processor, although that’s not what it was called back then. It was called a microprogrammed state machine back then, because HP was deeply into state machine design methodology in the 1960s and early 1970s. The microcode was woven into a rope memory, a sort of ROM version of a magnetic core memory that was also used in ICBM guidance and industrial control computers. The software ROM was a 32-kbit read-only memory made from a 16-layer printed circuit board (PCB). That’s not to say that the board held IC ROMs. The PCB itself was the ROM. It employed 32,768 inductive cells, organized as 512 64-bit words. Loveland’s PCB shop was barely able to manufacture this board because of the extremely small geometries and 16 layers.
From our perspective in the 21st century, it might not be apparent why HP used a PCB to create a 32-kbit ROM. It’s because IC ROMs had not yet been invented and the IC technology of the late 1960s was far from being able to create a 32-kbit ROM. It was clear that future desktop computer generations would need a better ROM technology, because the PCB ROM was already at its capacity limit.
Negrete recognized that his growth plans for Loveland would likely require some extra oomph from semiconductor manufacturing, so he hired Ed Shideler to start up an IC facility at HP Loveland. Shideler had worked at Fairchild and Transitron, so he had commercial semiconductor fabrication experience. He assembled a team of design engineers, process engineers, packaging engineers, and a couple of summer students to cobble together a bipolar semiconductor fab. The Loveland semiconductor lab’s early developments included some bipolar IC designs and thin-film devices such as laser-trimmed resistor networks and microwave devices. Loveland fab team members visited various HP fabs in California to pick up semiconductor fabrication know-how.
Two of the engineers on that HP Loveland semiconductor team were Larry Lopp and Virgil Laing. Lopp was one of the people traveling regularly to California to soak up HP’s existing semiconductor manufacturing knowledge. He could see that next-generation calculators would need much denser ICs and started looking at PMOS, then the highest-density semiconductor process technology, but he soon saw that PMOS ICs would be too slow to meet HP Loveland’s goals. Like IBM, HP Loveland needed fast and dense ICs.
The answer to this problem came in the form of a 4-page ISSCC paper that came sailing over Lopp’s bookshelf one day in 1969, tossed by Virgil Laing. “Look at this.” said Laing. The paper detailed IBM’s efforts in developing an NMOS IC process. Lopp read the paper and said, “We can do this.” Spurred by IBM’s NMOS paper, HP Loveland’s IC-development group planned on developing its own NMOS IC technology to get the speed and easy TTL interfacing offered by NMOS circuits.
Engineers at HP Labs in Palo Alto had been experimenting with NMOS technology and had developed some test devices. HP Loveland decided to start by trying to replicate the HP Labs technology. Tom Ligon, who had worked on manufacturing-yield problems with the HP 9100A’s PCB ROM board, obtained photo masks from HP Labs and tried to replicate the test devices. None of the first NMOS transistors fabricated in Colorado worked. They were all dead.
Ligon’s analysis of the problem suggested that the NMOS fabrication processes had to be at least an order of magnitude cleaner than bipolar processing to produce working devices, because the NMOS gate oxide was being contaminated with ions from the etching chemicals. Better cleaning procedures removed some of the contaminants, and working devices started to appear on test wafers. By 1970, the HP Loveland fab was making working NMOS ICs and had characterized enough of these parts so that Dave Maitland, another HP engineer on the NMOS project, was able to write an article about NMOS fabrication that appeared in the December 1970 issue of “Electronics” magazine.
Tom Haswell, who joined HP Loveland in 1970, got the job of finding a way to make NMOS ICs manufacturable. Although Ligon’s work had reduced the problems of initial MOSFET poisoning during fabrication, sodium contamination continued to plague the NMOS process. Sodium atoms, an ever-present contaminant, poison and disable NMOS transistors by riding the electric fields inside the IC and coming to rest in the MOSFET gates, altering the gate thresholds so that the NMOS transistors often failed to work at all.
Haswell eventually succeeded by specifying purer raw materials (especially aluminum for the interconnect, a problem that Frank Wanlass had identified at Fairchild eight years earlier) and by adding a back-gate bias voltage that provided an antidote to the sodium poisoning by increasing the MOSFETs’ threshold voltage. Although the NMOS transistors were still somewhat ill with sodium poisoning, the back-gate bias countered the effects of the sodium contaminants. Back-gate bias remained the industry’s solution to sodium gate poisoning until ion implantation was developed. Haswell’s success in taming the NMOS process led to HP Loveland’s development of the semiconductor industry’s first 4-kbit ROM IC. HP Loveland’s 9800 series (9810, 9820, 9821, and 9830) calculators had a voracious appetite for ROMs. In fact, the division created a lucrative business in selling add-on software in the form of plug-in option ROMs for its desktop calculators. As a result, the HP Loveland NMOS fab quickly became the largest NMOS production facility in the world.
By 1972, after HP’s Loveland Calculator Division introduced its second-generation HP 9820A and 9830A desktop calculators, HP knew that its computing machines had found a ready and growing market that would quickly draw competitors. Planning for next-generation machines started immediately. These new calculators would need even faster processors and higher-capacity ROMs, so HP Loveland’s IC facility started to develop the NMOS II process.
As he did with HP Loveland’s first NMOS process, Dave Maitland started developing design rules for the new NMOS II process. His valuable experience at ISSCC in 1969 had helped to launch Loveland’s NMOS efforts, so Maitland suggested that the NMOS II development team attend future ISSCCs, starting with the one held in 1972. The NMOS II team continued to attend ISSCC for several years, which was critically important given HP Loveland’s geographic isolation from Silicon Valley, the worldwide epicenter of chip development.
Development of the NMOS II process culminated in the introduction of the HP 9815A desktop calculator and the HP 9871 impact printer in 1975 and the HP 9825A Desktop Computer, introduced in 1976. The HP 9815A was based on an NMOS Motorola 6800 microprocessor and used 16-kbit NMOS II ROMs manufactured by HP Loveland. The HP 9871 impact printer used a single-chip, 59-instruction, NMOS II processor based on the 16-bit HP 2116 minicomputer architecture. The HP 9825A incorporated NMOS II ROMs and an 86-instruction version of the 16-bit HP 2116 minicomputer architecture, implemented in a unique 7-chip hybrid consisting of three NMOS II chips and four bipolar chips, all manufactured in HP Loveland’s fab. HP introduced a series of desktop computers based on iterations of these NMOS II chips, including the original HP 9825A/B/T, the HP 9845A/B/C, the HP 9831A, and the HP 9835A/B. This desktop computer family sold very well in the market, emboldening HP Loveland to become even more ambitious.
As if developing the world’s biggest NMOS fab near the beet fields of northern Colorado wasn’t big enough, the success of HP Loveland’s 98×5 desktop computer families spurred the development of NMOS III. The NMOS II process had been used to manufacture ROMs, 16-bit processor chips, and peripheral control chips. NMOS III would be used to develop single-chip 32-bit processors with multiprocessor capabilities (called FOCUS), ROMs, DRAMs, and peripheral components. HP Loveland’s fab was too small to accommodate this huge expansion, so HP’s Calculator Products Division built an entirely new fab east of nearby Ft. Collins, Colorado in 1977, relocated to the new site in 1978, and renamed itself the Desktop Computer Division.
The NMOS III program supported development of an extremely ambitious desktop computer called Dawn, which became the HP 9020 and HP 9000 Series 500 workstations. By this time, however, HP corporate was becoming interested in unifying the various computer architectures being used in its varied minicomputer, desktop computer, and workstation divisions. The costs associated with supporting so many proprietary processor architectures weighed down the entire company. HP as a corporation jumped to the PA-RISC (Precision Architecture – Reduced Instruction Set Computer) architecture, developed at HP Labs in Palo Alto. This move shortened the life of the FOCUS processor and the workstations based on that processor.
Although some PA-RISC microprocessors were fabricated in NMOS, the CMOS revolution, first ignited by fast CMOS developments at Hitachi in 1978, eventually caught up with HP. The last NMOS version of the PA-RISC processor appeared in 1989, and CMOS versions of PA-RISC microprocessors started appearing in 1990. These microprocessors were manufactured in HP’s Corvallis Oregon and Fort Collins fabs. HP’s NMOS III marked the final stage and a successful end to more than a decade of NMOS development in an unlikely, isolated part of northern Colorado.
References
Note: Information about the development of the NMOS II process came from personal discussions with Dana Seccombe, Geoff Chance, Dave Maitland, Bill Eads, Larry Lopp, and Tom Ligon.
George Chernoff, Dale L Critchlow, Robert H Dennard, and Lewis M Terman, “IGFET Circuit Performance—n-Channel Versus p-Channel,” IEEE Journal of Solid-State Circuits, Vol SC-4, No 5, October, 1969, p 267-271.
Joseph E DeWeese and Thomas R Ligon, “An NMOS Process for High-Performance LSI Circuits,” HP Journal, November 1977, p 26-32.
