The first six articles in this series described the history of the EDA industry from its earliest beginnings to becoming the multi-billion-dollar heart of the semiconductor industry. Starting with one-off tools developed by various systems companies for their R&D departments developing circuit boards and ICs, the commercial EDA industry was ignited by the spark that was the Design Automation Conference. It then progressed through various phases starting with CAD companies, CAE companies, and EDA companies. The evolved EDA companies grew through acquisition, and when there were very few small EDA startups left to gobble up, the big three EDA players (Cadence, Mentor Graphics, and Synopsys) entered the IP business and started acquiring companies in that domain as well.
As a result of this evolution and acquisition, EDA design flows are now so complex that the Electronic System Design Alliance (ESDA) recognizes more than 60 different types of tools and IP used in IC and PCB design flows. I call the sum of these different types of tools and IP the EDA layer cake. This article discusses those layers, as defined by ESDA. Note that different design flows for different types of ICs made with process nodes contain different sets of layers, however the total number of layers presents quite an impressive stack of tools for design teams to use.
In his YouTube video seminar for Stanford University’s EE380 class, titled “Electronic Design Automation and the Resurgence of Chip Design,” Raúl Camposano, CTO of Silvaco and a partner at semiconductor startup incubator Silicon Catalyst, summarizes the ESDA’s five categories for EDA tools:
1. EDA Services, which provide training and consulting for companies that need help with the EDA layer cake.
2. Computer Aided Engineering (CAE) tools, defined as IC design tools working at the transistor level and above. This category includes gate- and system-level design tools.
3. Printed circuit board (PCB) and multi-chip module (MCM) design tools, which get little attention in the IC-centric EDA world today. However, these tools remain essential for system design and all the major EDA vendors provide PCB design tools.
4. IC Design and Verification tools for the physical design of ICs. These tools generate the IC layouts and layer masks needed for fabrication.
5. Intellectual Property (IP), a segment that did not exist 30 years ago but is now the largest of the five categories according to Camposano. IP blocks include processors, memory, and I/O (USB, Ethernet, WiFi, etc). Currently, noted Camposano, Arm is the most successful IP company, thanks to the cellular phone industry’s nearly universal adoption of Arm processors.
Although these five groups are useful for categorization at the 50,000-foot level, they mask the complexity of ESDA’s 60-layer cake that has become EDA, so here’s a more detailed and slightly collapsed itemization with some very abbreviated versions of ESDA’s descriptions:
1. Services
1.1 Consulting services for modified or completed electronic designs, including semiconductor or semiconductor intellectual property (SIP) products, PCBs, modules, systems, libraries, verification, or retargeting.
1.2 Custom development for tools, design environments, product data management (PDM), and component information systems (CIS) services for customization of design tools and design environments.
1.3 Training services for design, design methodology, design languages, and use of EDA tools.
1.4 Other services.
2. CAE Tools
2.1 Electronic system level (ESL) design, synthesis, and verification tools for modeling, simulation, creation, or functional and performance analysis of system-level designs.
2.1.1 ESL design tools used to model, develop, debug, analyze, simulate, and visualize the functional behavior of a design (or parts of a design) modeled at high abstraction levels.
2.1.2 ESL synthesis tools that transform high-level descriptions written in C/C++, SystemC, or similar high-level input design abstractions into RTL descriptions.
2.1.3 ESL verification and ESL virtual prototyping tools for simulating and verifying the functionality and performance of system-level designs.
2.2 Design-entry tools for creating designs using hardware description languages (HDLs) including Verilog and VHDL, Boolean equations, high-level graphical methods, schematic editors, or some combination of these methods.
2.3 Logic Verification
2.3.1 RTL simulation tools including simulators and integrated simulation tool suites used to verify logic designs using one or more RTL languages (VHDL, Verilog, SystemVerilog, etc).
2.3.2 Dynamic verification and auxiliary RTL simulation tools that assist RTL simulators with verification.
2.3.3 Hardware-assisted verification tools including hardware emulators and accelerators.
2.3.4 Other logic verification and simulation tools (Including gate-level simulators).
2.4 Analog and mixed-signal (AMS) simulators
2.4.1 AMS simulators for simulating analog or mixed-signal designs.
2.4.2 Library characterization tools for characterizing standard cells, I/O cells, cell macros, and memory IP.
2.4.3 RF simulators that simulate circuit- and system-level RF/high-frequency/ microwave designs.
2.4.4 EM solvers including planar and 3D EM solvers that model and analyze the electrical characteristics of physical geometries and structures.
2.5 Formal Verification
2.5.1 Equivalency checkers that use formal techniques to verify the functional equivalence of a design as it is transformed from one design stage to the next, including RTL-to-RTL, RTL-to-gate, gate-to-gate, etc.
2.5.2 Property checkers that use formal analysis techniques to verify design properties such as assertions, assumptions, constraints, etc.
2.6 Analysis Tools
2.6.1 IC/ASIC static-timing and signal-integrity analysis tools that calculate delays and detect timing violations in a digital design. Also includes software tools that analyze electrical signal behavior in IC wiring networks including crosstalk and substrate noise analysis.
2.6.2 IC/ASIC power analysis and optimization tools that analyze, optimize, or diagnose power consumption and IR drop problems.
2.6.3 IC/ASIC transistor-level simulation and analysis tools that accept a SPICE netlist and perform timing or power analysis for designs with one million or more transistors.
2.6.4 Analog and high-frequency IC/ASIC analysis tools that analyze the results of AMS and RF simulators.
2.6.5 Other IC/ASIC-related analysis tools that analyze electrical, thermal, EMC, power, and timing related to IC wiring networks.
2.7 Design-for-Test and Test Automation Tools
2.7.1 Automatic test pattern generation (ATPG) tools for full-scan, partial-scan, and non-scan designs.
2.7.2 Built-in self-test (BIST) tools that insert circuitry or IP blocks to perform BIST functions for memories, random logic, mixed-signal circuits, etc.
2.7.3 Scan tools that insert internal scan circuitry to support ATPG, BIST, or IEEE 1149 boundary-scan circuitry.
2.7.4 Fault simulation and other test tools that simulate and grade fault patterns.
2.8 Synthesis tools that convert high-level electronic design descriptions to lower abstraction levels such as gate-level designs.
2.9 Other CAE hardware and software.
3. PCB & MCM Layout Tools
3.1 PCB schematic entry tools including schematic editors and schematic-capture tools.
3.2 PCB analysis tools that analyze electrical, thermal, EMC, power, and timing related to PCB wiring networks and related designs.
3.3 IC package analysis tools that analyze electrical, thermal, EMC, power, and timing related to wiring networks in IC Packages, multi-chip packages, or MCMs.
3.4 Other system interconnect analysis tools that analyze electrical, thermal, EMC, power, and timing related to wiring networks in cables, cable harnesses, connectors, sockets, and optics.
3.5 PCB computer-aided manufacturing (CAM) tools that produce manufacturing-ready board layouts including multi-board panelization.
3.6 PCB physical design tools including rule checking and photoplot output.
3.7 IC package physical design tools for placing physical components and/or routing interconnect signal traces on IC packages or multi-chip package assemblies.
3.8 Other physical design tools for non-PCB or IC package designs including cables, harnesses, connectors, sockets, and optics.
3.9 Library and design data management tools for designing physical interconnect systems and design libraries.
3.10 Other PCB and MCM hardware and software.
4. IC Physical Design & Verification Tools
4.1 Physical implementation tools for placement and routing of IC circuits including tools for designing gate arrays, embedded arrays, standard cells, and irregularly sized macro- or mega-cell blocks.
4.2 IC full custom layout tools for hand-crafted full-custom ICs that do not employ standard-cell design methodologies. These tools include polygon editors, symbolic editors, and compactors.
4.3 IC layout verification tools to ensure that an IC design does not violate any fabrication process rules. This category includes electrical rule checkers (ERC) and layout-versus-schematic (LVS) checkers.
4.4 Parasitic extraction tools that translate IC layout data into networks of electrical circuit elements (transistors, resistors, and capacitors) and parasitic elements (interconnect capacitance, resistance, and inductance) to enable the modeling of the IC design’s timing, power, and signal behavior.
4.5 Reticle enhancement technology (RET) tools including optical proximity correction (OPC) and phase-shift mask (PSM) tools that modify an IC design for a specific manufacturing process node.
4.6 Technology CAD (TCAD) tools that simulate, analyze, and optimize device and process parameters during semiconductor process research and development.
4.7 Mask data preparation tools that modify full-chip production designs by transforming the physical design’s layout into the various modified mask layers required for IC manufacturing.
4.8 IC yield enhancement tools that modify a physical layout to avoid manufacturing process vulnerabilities and improve chip yield.
4.9 Other IC/ASIC and FPGA physical design and verification tools.
5. Semiconductor Intellectual Property (SIP)
5.1 Tools used in the generation, creation, packaging, and management of SIP.
5.2 Macrocells and Cores
5.2.1 Logic libraries and standard cells, which are the building blocks and elements used to assemble or compile a cell-based IC design.
5.2.2 Memory IP including static, dynamic, and non-volatile memory.
5.2.3 Analog and mixed-signal blocks including ADCs, DACs, comparators, amplifiers, detectors, pulse compressors, signal sources, switches, PLLs, VCOs, voltage references and regulators, pulse-width modulators, filters, couplers, mixers, and analog multipliers or dividers.
5.2.4 Interface and peripheral blocks (in software or RTL form) that conform to recognized I/O standards including PCIe, USB, Ethernet, Bluetooth, WiFi, and DDR SDRAM.
5.2.5 CODEC and cryptographic blocks including encoders, decoders, modulators, and demodulators.
5.2.6 Graphics, imaging, and audio blocks.
5.2.7 Processor IP including general-purpose microprocessors, configurable microprocessors, and dataplane processors.
5.2.8 Subsystem IP composed of more than one IP block to form a subsystem or platform.
5.2.9 Test functions for debug and self-test.
5.2.10 DSP functions.
5.2.11 Other macrocells and cores.
5.3 Verification IP including models, monitors, test suites, testbenches, assertions, and checkers.
5.4 Embedded software including real-time operating systems, software stacks and drivers, and applications software.
ESDA’s EDA layer cake reflects the need to bring some order to the result of more than four decades worth of tool and IP development by the major EDA players and countless EDA and IP startup companies. It’s a deep and complex mix of products and services offered to IC independent device manufacturers (IDMs), fabless IC companies, semiconductor foundries, and systems companies. However, even after more than 40 years of growth, the entire EDA market is currently worth about $14 billion annually and now grows at the same rate as the semiconductor industry as a whole. Consequently, the major EDA players are presently looking for ways to break out of the electronics market and into even bigger arenas to support the growth rates they’ve enjoyed in prior years. That’s the topic of the eighth and final article in this series.
References
Raúl Camposano, Stanford Seminar – Electronic Design Automation and the Resurgence of Chip Design, February 6th, 2019
