Back in the 1980s, chips were designed with schematics. There was a comprehensive design tool flow to support schematic-based methodology, and the world had three big EDA companies – Daisy, Mentor, and Valid – whom most folks simply referred to as “DMV”. Those three companies thrived on the tools that defined that schematic-based flow – schematic capture, gate-level simulation, timing analysis, place-and-route, and design-rule checking. Life was good, the world was stable, and folks made some decent chips.
Unfortunately, Moore’s Law kept going. Designs got bigger and schematics got unwieldy. We needed a new thing, and that new thing was language-based design.
While DMV were off trying to invent the next generation of schematic-based tools, a new company called Synopsys brought logic synthesis technology out of the lab and commercialized it. That product, Design Compiler, revolutionized chip design by raising the fundamental design abstraction level. It also shook the EDA industry at its roots. By the time the dust settled, we still had a “big 3” EDA landscape, but now the players were Synopsys, Mentor, and Cadence.
Over the following decades, chips have been designed with hardware description languages working primarily at the register-transfer level (RTL). Synopsys, Mentor and Cadence (nobody seems to call them “SMC”) have all thrived by marketing and supporting commercial tools to facilitate RTL design and verification. This RTL flow has evolved in much the same fashion as schematic design before it. It has grown steadily faster, more efficient, and more reliable. But, Moore’s Law has still been busy at work. Even current RTL methods are becoming unwieldy with the massive SoC designs being created today.
We need a new thing again.
This time, the “new thing” isn’t quite as cut-and-dried as the transition from schematic to RTL. You see, as system-on-chip design has matured, it has raised its own abstraction level in a fairly natural and understandable way. While our chips now have billions of transistors, a lot of those transistors are busy being things like – memory. Memory doesn’t tax our RTL methods. We plunk down a big ‘ol block-o-RAM, throw in a little configuration, and we’re basically done with that part. Similarly, a lot of our design is made from pre-designed blocks like processors, busses, and common peripherals. Except for the folks who actually work at ARM, this part of our design doesn’t really strain our RTL methodology either. So a large portion of any SoC design will probably be a big, multi-core computing system with processor, peripherals, and memory. None of that really presents much of a challenge for today’s design tools.
But that part of the design isn’t where we differentiate. As expensive as each new chip is to design today, we’d better have a really good reason for creating a new one. Whatever that reason is will not be contained in the processor, peripherals, and memory. That reason will be our value-add – our differentiation. It is here that we are now in need of our “new thing.”
Since about the 1990s, many people have believed that the new thing would be some form of high-level design. “Behavioral synthesis,” “ESL,” and “high-level synthesis” have been catch-all terms applied to a wide range of failed and semi-successful attempts to raise the level of design abstraction above RTL. In high-level design, our source code is generally something like C, C++, or SystemC. Unlike with RTL, we do not specify all of our register-level timing explicitly. Instead, we give only the timing constraints that are required for interfacing with the outside world, and the tools are left with the flexibility to move detailed timing around in whatever way best accomplishes our design goals.
Many start-ups have been founded with the goal of bringing high-level design tools up to commercial standards. Most of them have now been acquired by larger EDA companies – their portfolios of cutting-edge tools often left on the cutting room floor as their engineers, ideas, and customers were absorbed into the massive machinery of the big 3.
One of the last remaining companies in that scene is Calypto. Even though Calypto is now partially owned by Mentor Graphics, the company continues to operate and sell independently. Calypto brings three important components to the high-level design party: high-level synthesis -“Catapult”, sequential logic-equivalence checking – imaginatively named “SLEC”, and RTL power optimization – “PowerPro.” These three simple-sounding components complement each other and together form a foundation for approaching the design of the differentiating parts of our SoC at a higher level. Together, could they transform modest little Calypto into the next Synopsys?
It turns out that power is at the root of all this.
Today, mobile design drives technology. In mobile design, power is king. We have to be able to do our digital magic with as little energy from those tiny little lithium cells as possible. That means every part of our design has to be done with power consumption in mind. For the SoC backbone – processor, peripherals and memory – most of that power optimization is out of our hands. It was done back in the labs at the IP companies that sold us the stuff. Similarly, since we’re talking SoCs here, most of the functionality will ultimately be delivered as software. What we are left with – our differentiating hardware – is almost always made up of functions where two things are simultaneously critical: power and performance.
This transformation of the design process begins with Catapult High-level synthesis (HLS). Catapult allows you to design hardware using ANSI C, C++, or SystemC. Your design at this level will be much smaller than the RTL equivalent. How much smaller? If you’re using untimed C++, dramatically smaller. A couple hundred lines of C++ could easily yield ten thousand lines of same-function RTL.
Writing a few hundred lines of C/C++ instead of tens of thousands of lines of RTL may sound like a great deal, but that’s just the tip of the iceberg. That C/C++ description carries virtually no hardware architecture specification, while the RTL version of the same design carries a very specific hardware architecture. As a result, you can do massive architectural tradeoffs during high-level synthesis that would not be possible with RTL. By exploring various architectures, you can quickly come up with the best combination of power, speed, latency, area, and other critical variables – all without having to rewrite your design source.
Catapult customers find what you’d expect – a significant reduction in design time compared with RTL methods. They also report that they are able to achieve better results in terms of power, performance, and cost. That trend represents a major breakthrough in the process of taking HLS into the mainstream of design. For years, the challenge for HLS was “come close to hand-coded RTL in quality.” Today, customers regularly report that HLS has surpassed their best hand-coded results.
Just getting great results isn’t enough to make it into the mainstream, however. Real-world design means that HLS must be able to handle designs with complex interface protocols, weird memory schemes, and funky timing constraints. Blocks designed with HLS need to play nicely with RTL blocks and various combinations of IP from different sources. HLS needs to be able to handle a wide variety of design blocks, including datapath-dominated, control-dominated, and crazy combinations of the two. Finally, it seems, HLS has cleared most of these hurdles well enough that a large number of companies are beginning to adopt it for production design.
Raising the design abstraction level creates a new verification problem, however. We need to be able to verify that the thing we end up with does what our original code says it should do. While our high-level code will certainly execute much faster than RTL simulation, the task of mapping from the final netlist back upstream to that original source for verification purposes is much more difficult. Here, Calypto is doing interesting work in combining the power of SLEC equivalency checking with Catapult HLS to verify that the output fulfills the requirements of the input.
Of course, it takes a lot more than rolling out a disruptive technology to make the leap from EDA startup to diverse “big 3” status like Synopsys did with Design Compiler. Mentor may have made an astute move acquiring an interest in Calypto and moving the Catapult technology (originally developed at Mentor) into Calypto to incubate. Having an engineering, sales, and support team focused exclusively on deploying the new technology could give Calypto’s disruptive tools the extra oomph needed to jump from early-adopter fanatics into boring-old mainstream, cash-generating production. At the same time, the close relationship with Mentor gives Calypto a good connection to the rest of the design flow, without Calypto having to become a full-line EDA player on their own.
