feature article
Subscribe Now

Aggressive Hard Drives

SPIE Litho Paper Combines DSA and NIL

When I go to the SPIE Litho conference, I normally expect to hear the latest on the technologies that are next in line for getting us past the current lithography hurdles. At this point, that might be EUV (or will it?).

But it can be even more fun to keep track of those outrageous ideas that haven’t quite managed to get a “Yes, this can work” check mark next to their names; people are still pushing and pulling to figure out if they will meet our needs two or three nodes from now.

So this year I figured I’d go see what was up with both directed self-assembly (DSA) and nanoimprint lithography (NIL). Both of these have appeared and surged over the last couple of years, and I figured I’d be reporting some new refinements of what works and what doesn’t for various bits and pieces of the processes. And I took notes from this session and that to fashion into something that, with luck, might resemble an interesting story.

But here’s the thing with some of these conferences: You’re presented with a pile of sessions. Some conferences organize them better than others. IEDM does a particularly good job of asking their session chairpeople to identify the most meaningful sessions ahead of time for the press so we get a clue where to focus. On the other end of the spectrum, some simply list all their papers in chronological order. So after 15 minutes of scrolling through what can be mind-numbing titles (technical papers are not known for eye-catching headlines), you kind of glaze over and they all start to sound the same.

Typically you’re somewhere in between, so you can still find yourself realizing too late that there was a session you really should have attended that you didn’t. (To be fair, these shows have varying focus on press… SPIE in particular doesn’t provide proceedings until a couple of months after the show, making timely detailed coverage impossible unless you record the whole dang thing… but their focus is on their engineering audience, not press.)

All of which is a very roundabout way of saying that, just as things were winding down, I discovered that there was a paper I wished I had seen. It didn’t simply report on some advances in DSA, nor did it merely move NIL forward. No, it reported on actual devices built using both DSA and NIL, documenting lessons learned along the way. The result wasn’t quite production-worthy, but it represented a big jump, albeit in a very specific area: hard disk drives.

The company was HGST, and they were kind enough to answer my questions and send follow-up information after the fact. Their requirements were different from what an IC designer might need – some of which gave them a break, but some of which were more strenuous than what IC designers demand.

So let’s start by reviewing the problem HGST is trying to solve. These guys want to make a disk with as much storage as possible. Traditionally, continuous magnetic media has been used, with individual domains defining bits (or, more specifically, transitions between polarizations – or lack thereof – defining the bits). The new Big Idea is to create isolated islands of magnetic material. Each one would be a bit. This approach is referred to as bit-patterned media (BPM).

The challenge is in the sizing: we’re talking the 20-nm range – full pitch, not half pitch; we’re talking now, not three nodes from now. That requires lithography that ICs won’t be needing for a while.

The arrangement of islands is often done as “hexagonal close-packed” (HCP), which is essentially a tight packing of dots; any dot would have six neighbors around it. But for the purposes of compatibility with existing hard drive read heads, a rectangular island that’s slightly wider that it is deep (i.e., a bit area ratio – or BAR greater than one, likely less than 2 or 3) would be preferable. So while some of their early work reflected an HCP layout, they changed at some point to rectangular. (Did I mention that there will be acronyms?)

So even though they’re looking for dimensions that are far more aggressive than will be used on an IC, they also have a very regular pattern – no funky shapes or FinFET nonsense that require not only more work to master, but also EDA help to define the DSA guides. Just an array. A circular one, to be sure, so there is a circumferential dimension and a radial dimension.

The other critical requirement is cost: they can afford perhaps $1 extra per disk for this new approach. So everything has to be super cheap. The thing is, production using the kinds of lithography that can deliver these dimensions can be slow and expensive. So the idea is to take that time to make an expensive master and then use that master for replication using nanoimprint technology (done in partnership with Molecular Imprints).

In fact, since a NIL template is generally expected to be able to make 10,000 copies before wearing out, the master would make 10,000 working templates, and each of those working templates would be used to make actual disks. A single master would then enable 100 million disks.

That then gives us two distinct aspects to manufacturing: creating the master and replicating from the master.

Yes, Master.

They used DSA to create the master, opting for chemo-epitaxy for guiding the self-assembly. As a reminder, this means that chemical traces are laid down on the substrate as a guide rather than using guiding “walls” (“grapho-epitaxy”). This allows the pattern to lay over the guides uninterrupted; in other words, the guides do their job, but they don’t get in the way.

So the high-level process is then:

1.  Create the guides using e-beam lithography (slow, but used only for a master).
2.  Perform the DSA step
     a. Deposition
     b. Annealing
     c. Development
3.  Transfer the DSA pattern to the substrate.

The DSA process requires more discussion; it might seem like this is a well-defined thing, but really, it’s still a wild, wooly world out there, and everyone is trying to figure out the right way to do it. There are lots of options, and along the way, HGST ended up trying a number of variations. They reported on some of the results (keeping some for themselves), working with researchers from the University of Chicago for parts of it. I won’t go into tons of detail, but some of the considerations are worth mentioning.

First is the choice of block copolymer (BCP). There are a several choices available, most of which are diblock copolymers, meaning two adjoined polymers that will self-assemble. PS-b-PMMA (polystyrene and poly(methyl methacrylate) – the “b” stands for “block”) seems to be most common. Less researched, but also possible, are triblock copolymers – three sets of polymers. In some cases, it’s only two polymers, but both ends of the middle polymer are bonded to the other one: P2VP-b-PS-b-P2VP is an example of this (P2VP is polyvinylpyridine… I have no idea what the 2 is for… I don’t come up with these things).

They chose PS-PMMA because it’s easy to develop (that is, it’s easy to remove one of the two polymers selectively) and because they form perpendicular lamellar structures. The downside with this choice is that it’s extremely difficult to achieve a pitch less than 25 nm; some have gotten as low as 18 nm. They wanted more headroom to define the small island domains, so, as we’ll see, they used line doubling in the transfer phase.

Having selected PS-b-PMMA, the DSA process was relatively straightforward: deposit the BCPs, anneal to let them self-segregate, and then develop – meaning remove one of the two (the PMMA) to leave a pattern defined by the PS.

The following step – transferring this pattern into the substrate – is where a number of options were exercised by the team.

  • Direct etch: the PS acts as a mask, and the pattern is etched into the substrate.
  • “Cr lift-off”: chromium is deposited, and it’s lifted off with a wet strip. The portion over PS preferentially comes off, leaving the portion that’s directly on the substrate (where the PMMA was removed) to act as an etch mask. This did not perform well for them at 25 nm and was abandoned.
  • “Cr+SOG lift-off”: like Cr lift-off, but glass is spun on over the chromium (“SOG” = “spin-on glass”). This worked where the Cr lift-off didn’t.
  • Block Selective Infiltration (aka Selective Infiltration Synthesis): atomic-layer deposition (ALD) methods are used to expose the undeveloped surface to trimethyl aluminum (TMA) and then to water vapor. This leaves aluminum oxide preferentially over – or actually absorbed into – the PMMA. The PS is etched away, leaving the aluminum oxide as a hard mask.
  • Electrodeposition: electroplating a metal (like nickel over a tungsten seed) after developing the BCP; the metal lies between the PS lines; the PS is then removed. This requires a conductive substrate.
  • They also worked with triblock copolymers, getting pitch down as low as 16 nm.

Makin’ Copies

Given a master, there are some options for making the copies. The first detail here is one of “tone reversal.” To my mind, this is an issue of whether your imprint template acts as a negative or positive. Will the ridges, which will become “channels” when pressed into resist, ultimately define raised or depressed regions? They found that reversing the tone – where the template ridges end up being depressions –provided the best results.

The other decision they made was to split the imprint process into two: one for the circumferential lines and one for the radial lines. This means they had to make two masters (or “submasters”). Because the islands were going to be wider (that is, along the radius – meaning that the circular tracks would be slightly wider than the size of the island along the track), then they could use less aggressive technology for the circumferential template.

For the radial template, the PS-b-PMMA choice couldn’t get them as tight as they wanted. So they used sidewall spacer doubling, much as is done for ICs, to get down to a reliable 7-nm half-pitch – the smallest features yet reported for such a process.

Actual results

Having messed about with all of these different approaches, they did achieve success with the following choices:

  • Silicon master; quartz working masters
  • PS-b-PMMA
  • 27-nm pitch circumferential submaster, using Cr+SOG lift-off; no line doubling
  • 20.5-nm pitch radial submaster, created with 41-nm pitch lines that were then doubled; transfer was by direct etch, although they subsequently developed better alternatives.
  • The BAR was about 1.3
  • When imprinting onto a disk containing a magnetic film layer, the circumferential lines were imprinted first, followed by the radial lines, before etching out the film to create magnetic islands.

You can find many more details in their paper when the proceeds are available; this is paper 8685-21, titled “Generation and Transfer of Large-Area Lithographic Patterns in the ~10-nm Feature Size Regime”, Albrecht et al.

One thought on “Aggressive Hard Drives”

Leave a Reply

featured blogs
Nov 15, 2024
Explore the benefits of Delta DFU (device firmware update), its impact on firmware update efficiency, and results from real ota updates in IoT devices....
Nov 13, 2024
Implementing the classic 'hand coming out of bowl' when you can see there's no one under the table is very tempting'¦...

featured video

Introducing FPGAi – Innovations Unlocked by AI-enabled FPGAs

Sponsored by Intel

Altera Innovators Day presentation by Ilya Ganusov showing the advantages of FPGAs for implementing AI-based Systems. See additional videos on AI and other Altera Innovators Day in Altera’s YouTube channel playlists.

Learn more about FPGAs for Artificial Intelligence here

featured paper

Quantized Neural Networks for FPGA Inference

Sponsored by Intel

Implementing a low precision network in FPGA hardware for efficient inferencing provides numerous advantages when it comes to meeting demanding specifications. The increased flexibility allows optimization of throughput, overall power consumption, resource usage, device size, TOPs/watt, and deterministic latency. These are important benefits where scaling and efficiency are inherent requirements of the application.

Click to read more

featured chalk talk

Vector Funnel Methodology for Power Analysis from Emulation to RTL to Signoff
Sponsored by Synopsys
The shift left methodology can help lower power throughout the electronic design cycle. In this episode of Chalk Talk, William Ruby from Synopsys and Amelia Dalton explore the biggest energy efficiency design challenges facing engineers today, how Synopsys can help solve a variety of energy efficiency design challenges and how the shift left methodology can enable consistent power efficiency and power reduction.
Jul 29, 2024
80,862 views