We think of logic as an electrical phenomenon. In the past, memory was a magnetic domain, then it shifted to electronic, and, with the further development of MRAMs, it’s coming back around to magnetic again.
Crocus has been riffing off of their magnetics to the point where their MLU technology has some potential to make inroads not only into memory electronics, but even into logic. They’ve been pretty quiet about the details of the technology, and there are still things they’re not talking about publicly. But they are waxing a tad more loquacious with respect to the promise of the MLU technology. Granted, it’s only one side of the story (assuming there’s another – there may not be), but, as they tell it, the benefits accrue on a number of levels.
As a quick review, traditional MRAM technology involves two magnetic layers: one is fixed or “pinned”; the other is changeable. The resistance of the current path through the two combined layers will depend on whether they’re both magnetically aligned or counter-aligned (officially, “parallel” and “anti-parallel”); measuring the current decides the state of the cell.
The write process can be enhanced by raising the temperature of the magnetic junction; this is so-called thermally-assisted switching, or TAS. This makes the cell both more stable and more scalable.
Most recently, Crocus announced that the pinned reference layer could, in fact, be made un-pinned, so that now both magnetic layers are writeable. The reference layer is then referred to as a “sense” layer. This becomes the basis for what they call their Magnetic Logic Unit, or MLU.
All of this we’ve discussed to some degree in prior articles.
In a conversation with Crocus’s Barry Hoberman following an announcement of work that Crocus was doing with IBM, we discussed why they are excited about this technology, beyond the fact that MRAMs, even in their most basic form, are fast to read and write and, with no specific wear-out mechanism, have infinite endurance.
But there are several other fronts on which they see benefits from their MLU technology.
The first is the fact that they can implement multi-level cells (MLC). MLC technology is pretty standard in FLASH memory; there it’s made possible not by measuring simply the presence or absence of charge on a floating cell, but by detecting various amounts of charge, requiring very sensitive sensing. But that won’t work for an MRAM cell, since we’re not measuring charge. What will work? I don’t know. Because Crocus isn’t saying at this point. All I know is that they say they can do up to 8 bits’ worth of MLC (that’s 256 values), with a “slight” degradation in performance for the higher bit counts.
In other discussions of MRAM technology, you may see references to multiple magnetic layers, and it might be tempting to think of this as the way that MLC can be done. But that’s not how Crocus does it. They say they can do an MLC cell with only the two magnetic layers. And then they can do multiple layers in addition to that. This means that if they do two layers of 8-bit MLC, they have a 16-bit equivalent cell.
They can use this to create a NAND memory configuration that is random access, with a read time that’s equivalent to standard MRAM speed and a write time that’s around 50% slower than standard MRAM write speed (but still an order of magnitude faster than CMOS FLASH). Combined with multi-layer technology, they can put four magnetic tunnel junctions (MTJs) on one layer or two on each of two layers. (And this has me wondering if MLC means per cell or per junction… since you can have more than one junction on a layer…)
As a result of the combination of MLC and stacking, the 25F2 cell size for a single-level single-layer NOR-configured cell can come down as low as around 1F2 for a NAND configuration with 8-bit MLC and 2 layers.
The fact that the MLU can implement a native XOR gate opens up a whole new range of options for what is, essentially, logic comparison or hardware search. Things like translation look-aside buffers (TLBs) and content-addressable memories (CAMs) can be 20-40 times as dense as is normally possible. For a CAM cell, for example, they claim a 20F2 bit as compared to the CMOS equivalent of 250-500F2.
Lookup tables for computation can be 25 times denser than is possible with CMOS memory. And they describe a way of implementing tamper-resistant memory that cuts authentication time by 90% and includes an instantaneous self-destruct capability.
For all of these applications, the cell has the benefits of non-volatility, allowing live start-up. And the fact that it is impervious to alpha particles eliminates a significant source of soft errors.
The capabilities up to this point have involved new functions or density of functions. MLU technology also helps manufacturing.
The reference layer in a standard MRAM cell must be set during manufacturing in what is called a magnetic annealing process. This is an expensive step that requires the devices to be heated up, exposed to a very high magnetic field, and then cooled to freeze that alignment in place. It’s kind of like the magma that seeps up in the middle of the Pacific, aligning itself to the earth’s magnetic field as it cools.
This magnetic annealing step contributes up to 40% of the incremental capital required to build these devices. Platinum is also required as a material for the reference layer. Because MLU technology has no reference layer, all of this goes away, providing a manufacturing cost benefit.
In addition, because the value of the cell is no longer being read against some fixed reference, the cell is now “self-referencing.” It’s essentially taking what was a common-mode read mechanism and turning it into a differential-mode mechanism. This makes it much more tolerant of “noise” and variation in processing.
Specifically, when a pinned layer is used, the absolute value of the resistance of the MTJ needs to be at 1 kΩ and 2 kΩ for the two read levels. For this to be solid and reliable, the distributions have to be extremely tight around those two values. The separation between the two distributions needs to be around 16-20σ of the coarser of the two distributions to ensure that the two levels can be reliably discriminated.
This requirement originates in the fact that, in a standard MRAM cell, it’s the absolute value of the resistance that matters. With an MLU cell, it’s the relative resistance. Many cells that would fail on an absolute basis could pass in an MLU cell. In other words, there’s an enormous yield benefit to using the differential self-referencing read mechanism instead of the common-mode absolute-value mechanism.
Finally, without a pinned layer that might be disturbed when too hot, the operating temperature for these chips can be raised above 200 °C. High-temperature CMOS memory is hard to find because of the accelerated leakage as you bring on the heat; MLU technology can help to address those applications.
All of this, of course, has to do with the implications of the underlying technology. Crocus isn’t saying exactly what they plan to do commercially with it. They’re going to work with IBM to get all of this ready for prime time, and then they’ll be making it available to the new fab that’s going up in Russia.
But if all the things they say should be possible end up panning out, well, there may be a bit of a shake-up in the memory world.
There’s lots of interesting new memory technology afoot in the early stages of development. What kind of exotic stuff are you looking at?
Whenever I see new variations of memory technology, my first thoughts tend to migrate in the direction of FPGA configurations.
OK, I’ve been a fanatical fan of FPGA enabled design strategies for quite some time, so I have to admit a bit of a bias toward such notions . . . but a magnetic FPGA logic structure could offer a unique set of properties not possible (or at the very least, inconvenient to implement) via any other means.
I’m just curious if anyone else here had similar thoughts, or if such ideas are too far outside the box at the moment.