The late and very greatly missed Douglas Adams once wrote:

1) everything that’s already in the world when you’re born is just normal;

2) anything that gets invented between then and before you turn thirty is incredibly exciting and creative and with any luck you can make a career out of it;

3) anything that gets invented after you’re thirty is against the natural order of things and the beginning of the end of civilisation as we know it until it’s been around for about ten years when it gradually turns out to be all right –really.

Now this was over ten years ago, and he was talking about the way people were accepting, or not, the use of the Internet. But I was reminded about this quotation in Grenoble at the DATE Conference. Specifically, it was about users’ attitudes towards EDA tools. In the past, those who designed with schematics were resistant to using hardware description languages, today those who make their living hacking RTL code are resisting the system level tools.

The structure of the EDA world seems to be stable, with three big companies and a number of smaller companies, and with the bulk of designs being written in RTL. But this is a relatively recent phenomenon and could easily change tomorrow. In fact it is almost guaranteed to change, just as it has changed several times to reach this state.

Three things will influence the change: the increasing use of system level design tools, the increasing use of IP, and the increasing concentration of manufacturing into a small number of foundries. And all of these threads were present at DATE in Grenoble, France earlier this year.

One place in which they came together was during an executive session looking at the future of EDA and IP. Krisztian Flautner, VP of R&D for ARM, came up with an interesting picture of the future. He sees the EDA scene today as a three-legged stool: EDA is one leg, “star” IP companies (companies like ARM) the second, and the foundries are the third leg. None of the legs are pure-play, however. The foundries are offering IP, as are the EDA companies. The star IP companies are offering tools, as are the foundries. They all offer design services. In Flautner’s view, the current position is unsustainable, and he suggests that one scenario is that the foundries and the star IP companies will, between them, push the EDA companies out of the scene. (This ties in with an approach that I have heard floated, with various degrees of seriousness, that for all except the most leading edge designs, it should be possible to put together an SoC with IP and buses, providing the IP has integrated bus interfacing. In fact, this is, to a large extent, what you can do on the Xilinx Zynq Extensible Processing Platform.)

Naturally, not everyone on the panel agreed with Flautner. Both Ajoy Bose, President & CEO of Atrenta, and John Bruggeman, Chief Marketing Officer of Cadence, were sure that the EDA360 approach would ensure the survival of the “traditional” EDA companies. In simple to simplistic terms, EDA360 is the Cadence/Bruggeman initiative to broaden and extend the role of the EDA company, both extending into higher levels of abstraction, with what we have been calling ESL (Electronic System Level) tools, and broadening by providing much more IP and also meeting the increased need for software. When it was first announced last year, EDA360 looked a bit like a Cadence marketing initiative, but it does seem to have gained wider acceptance, and, to be fair, it does encapsulate some sensible ideas. Even Synopsys seems to reflect some of the views, with Joachim Kunkel, a Senior VP & GM, suggesting that we should begin to think, not of silicon with some software running on it, but instead look at an SoC as the execution platform for software to carry out a task. (It is rather like an interesting comment I heard years ago about DNA. From a human perspective, DNA is the mechanism for creating other humans. For DNA, humans are the platform for creating more DNA.)

In a private conversation later, Bruggeman was dismissive of any suggestion that the foundries would take over the tools business: he feels that the tool users want to retain foundry independence as much as possible.

Christoph Heer, a Vice President at Infineon, was presumably on the platform to reflect a major tool user’s perspective. One thing he is seeing is the way the foundries are taking on more and more roles, offering IP and design services. He also commented that where, in the past, many new ideas in the design chain came from point tools developed by start-ups — which were then bought by the larger players to integrate into their design chain, the start-ups today are mainly operating at the system level, with a very few operating at DFM (Design for Manufacturing) and similar lower levels.

This was certainly the case in the exhibition hall. Until around 2002, DATE was used by many companies as a curtain raiser for DAC. Today it is a shadow of that show, but this year exhibitor numbers were up and the show floor felt lively. Most of the companies exhibiting were small, European-based and frighteningly technical – with many offering tools for the system level or concerned with the higher-level architecture decisions.

What follows is a not-quite random selection from the people I spoke to. If I spoke to you and you can’t find your company here, my apologies, but there is only so much space available.

One niche that seems interesting is generating processors. I found two companies offering approaches to creating ASIPs (Application Specific Instruction-set Processors). Belgium-based Target has trademarked “The Third Tool in the Box” as a description of ASIPs, showing how they are bridging the gap between general-purpose microprocessors and hardwired datapaths. The idea is that there are some areas in an ASIC or SoC where developers want to retain flexibility in the final product — for example, to cope with evolving standards — but don’t want the expense and overheads of a full-blown processor. With Target, the developer describes the ASIP in nML, a proprietary description language. The description generates a complete SDK (Software Development Kit), including a C Compiler complete with assembler and linker, an instruction set simulator, a hardware generator for creating RTL to go into a standard tool flow, and a test program generator, all wrapped in a GUI.

A similar approach is available from Codasip, from Brno in the Czech Republic. The architecture language, called ISAC, allows generation of VLIW and Multiprocessor SoC architectures and is supported by a full range of tools, including compiler, de-compiler, test tools, and RTL generators.

An alternative approach to the same problem comes from Adicsys, based in a southern suburb of Paris. Their tool generates Synthesizable Programmable Cores to provide an FPGA-like fabric within the synthesizable RTL. Adding FPGA as IP blocks has been tried before, without success. The barriers have been the physical footprint of the IP, the speed of the fabric, and the inflexibility of the hard IP. The SPAs can be scaled to optimal size and are of comparable speeds to the rest of the device.

Another French company, this one based near Grenoble, is addressing the problem of accurate simulation of Analog/Mixed Signal designs. Spice, the workhouse for many years, operates at the transistor level and is running out of power for anything other than trivial devices. Asygn is promoting simulation at what the company is calling Analog System Implementation (ASI) level. This operates generally at the schematic level, and Asygn is talking about simulations that ran for 80 hours in Spice taking only 2 minutes in ASI mode.

Still looking at high level, in fact looking at even higher level, is Proximus, a German/Armenian company. Normally a sentence such as, “… solutions for System Level Design using a new computer paradigm to enable efficient development and use of today’s multi-processing compute capabilities,” would have me reaching for the “jargon explode” macro in my word processor.  But, despite the marketing speak, these guys have an interesting approach to building multi-processor systems. They start with a transaction-level model and work from there to map transactions to virtual platforms. Once these are running, they add the compromises needed for real life and those required to allow the designs to be mapped onto real platforms of CPUs, GPUs, and FPGAs etc.

Getting down and dirty with technical details were several companies. EdXact, from Voiron in central France, has sold its tools for parasitic extraction and analysis from netlists to ten of the top 15 semi companies since it was founded in 2004. Xyalis, based in Grenoble, specialises in mask data preparation. Its target is mainly, but not exclusively, people laying out Multi Project Wafers (MPW). And finally in this quick skim through the European companies is Munich-based MunEDA, which has a suite of tools, called WiCkeD, which is used for analysis and optimization of analog, mixed-signal, and digital designs. 

Ok, so at one end we have large companies debating the future of the industry and at the other end of the scale, small companies getting on with developing and selling new technologies and new ideas. Nothing new there. But is the EDA business going to have a future? Of course, but certainly not in the form it is in now. The current structure really isn’t sustainable, with the tools companies saying they are not getting enough for their products and the users complaining about the high price of tools. Icahn’s bid for Mentor, following the withdrawn Cadence bid last year, shows that outsiders are recognising that there are structural issues in the EDA industry. It seems to me that we will see increased use of system-level designs and increased use of IP, which will require improved IP from the many non-star suppliers. At some point in the design chain the specifics of the particular production process within a particular foundry will require very process-specific tools, and these will, probably, come from the foundries.

The existing companies who don’t recognise and accept this change will be squeezed. And who will be the winners and losers?  If I knew, I would be opening the savings jar and betting on the stock prices.