Hawaii is a different beast.

It may be part of the US, but things operate with mindset unfamiliar to the typical go-go American, as you’ll immediately discover when waiting to get your rental car.

They refer to it quaintly as “Aloha time.”

For instance, the caterer is supposed to set up at 1 PM. By 2 PM no one as showed up yet. Explanation? “They’re on Aloha time.”

Now, this is a problem only if the party is due to start at 2 PM. If, on the other hand, the party is going to start, well, when the party is ready to start, then it doesn’t really matter. Just relax, grab a little refreshment, and let things take care of themselves.

We can’t seem to manage that on the mainland. Here we schedule everything as tightly as practical. If something goes wrong with the schedule, it triggers a whole chain of scrambling, screaming, and rescheduling. An entire plan may fail if any of the pieces has a problem.

That’s what’s nice about Aloha time. You may not know when something’s going to happen, but it will happen. No sweating, purplish, apoplectic faces yelling at you. Just a pleasant island calm. Don’t worry. Be happy.*

Most electronic systems operate like the mainland. There is a schedule, and everyone is on that schedule. Things happen at prescribed times, providing a level of predictability and comfort. The problem with this is that everything needs to happen on time. Nothing is perfect, so you have to make some allowance for things being off. What with variation being what it is, this is getting harder and harder.

There are other issues. The very fact that there’s a central clock means that there is a huge spectral peak in the EMI emissions at that frequency and at derivatives thereof. Even with the clock domain proliferation going on, many of those clocks are derived from the original, so they still play with the same basic set of harmonics.

Another issue is power consumption. The clock must clock, whether anything is happening or not. We’re getting better about that; one of the main reasons for these clock domains is not for different clock frequencies, but rather so that we can shut off areas of the circuit and reduce power. But that’s a high-granularity power-saving technique. Within a domain, the clock will clock whether anything is happening or not.

There is another way to do things. A very much Aloha way at that. By using asynchronous logic. With asynchronous circuits, you eliminate the clock. Data times itself. There is no schedule. Things happen when they’re ready to happen.

Asynchronous logic has been around forever. You may recall seeing (and possibly shying away from) asynchronous automata courses in your upper division course catalog. Some of you may remember the PAL16RA8.

There was even an attempt at another asynchronous PAL that used self-triggering inputs to eliminate metastability by combining data and clock into a single signal, thereby eliminating setup and hold time; without those to violate, no metastability. That actually didn’t work out because, although the delay requirements were gone, they were replaced with – surprise! –  pulse-width minimum requirements, which, if violated, could trigger metastability. Oops. So that didn’t last.

Asynchronous approaches have often been feared. Visions of hazards and glitches and such. Worse yet, trying to debug things if they go wrong. Only the stalwart have ventured there. And only when there’s a benefit. Gone are the days of trying to achieve intellectual mastery by conquering the complex asynchronous beast. That doesn’t pay many bills.

More recently, a number of companies have rediscovered asynchronous logic, although the track record is spotty, and not necessarily due to issues with the concept. Achronix uses it for their high-speed FPGAs. Silistix uses it for their NoC technology. Or I should say, used. Their erstwhile website now says, “Coming soon, Punxsytrader.com.” Presumably this doesn’t refer to a new Silistix technology. Handshake Solutions and Elastix were developing chips and tools (respectively), but they ran afoul of the economic meltdown. Tiempo is still around.

Tiempo makes so-called delay-insensitive asynchronous circuits. Or call them Aloha asynchronous circuits. Things will work regardless of actual delays. This means that, when the voltage drops or rises far outside the range of what would normally work, the Tiempo circuit will still work. If the temperature goes to extremes (well, not too extreme), it will still work. If the process was varying a bit when built – say you get a Monday or a Friday chip – it will still work. Timing may be off, but it will work.

The fundamental element that makes this happen is called the Muller C-gate. And, in case you think this is some brilliant recent innovation, well, it is, but geologically speaking. It was invented by a guy named Muller in the 50s; it was used in the ILLIAC 2 ALU. So it’s been around the block a few times.

A C-gate is actually surprisingly simple. Picture a CMOS inverter. P-channel pull-up; n-channel pull-down. Now… simply add another pull-up in series with the existing pull-up and another pull-down in series with the existing pull-down, and drive the new transistors with a second input. This almost sounds like a NAND or NOR gate, except that, with those, one of the two added transistors goes in parallel, the other in series.

So this is an odd gate in that, as long as both inputs are high or low, the gate acts as a normal inverter. But if the inputs have different values, then it can’t pull up or pull down.

Now picture that output driving an inverter, with a weak feedback “keeper” inverter feeding the first inverter’s output back to its input. Basically, a memory cell. So now, if the inputs aren’t in a state to drive the value high or low, then the keeper maintains the existing state. The keeper is weak so that it can be overridden when a new value comes.

This C-gate has two basic capabilities, referred to as “rendezvous” and “memory.” The memory part you can probably figure out by now. The rendezvous part is less obvious. Let’s say that you’ve got a calculation to do that depends on two earlier calculations. Traditional design would have you figuring out delays and counting clock cycles and synchronizing everything so that you would know exactly when the data would be ready for the calculation.

With the C-gate, the two earlier calculations can rendezvous whenever they’re ready, and the subsequent calculation can then go forward. Let’s say one of them is done first; it sets a line high. But the other one isn’t done yet, so its line is low. That means that the C-gate simply maintains its old value. Once the second calculation is done, its line can go high, and, with both lines high, both calculations have checked in at the rendezvous point, and the C-gate now takes on its new value.

I sort of referred loosely to a “line” in that description. In fact, it could be a line. Tiempo uses a simple four-phase communication protocol involving simple request/acknowledge pairs to facilitate state machines. This communication can be done with single lines, since a “high” indicates active and a “low” indicates inactive. That is, the arrival of a high is the event that makes things happen.

But what about when you have data signals? In that case, both high and low have meaning; they’re data values, not an active/inactive indicator. For these, Tiempo one-hot encodes the single value into two wires. Both wires low means no data change. One wire going high indicates transition to a 1; the other wire going high indicates transition to a 0. As in the case of counting to 5 with the Holy Hand Grenade, both lines going high is “right out.”

Put these deceptively simple pieces together, and you can assemble some complex logic. Not that you’d want to do that by hand; tools handle the grotty bits for you. You can also place asynchronous islands within synchronous logic; they’ll synthesize the necessary interfaces to make sure they play nicely together.

For all this effort you get to eliminate your clock. Only signals that have to change do change. That reduces the amount of emission and spreads the spectrum out much more evenly. Power goes way down because you don’t have all kinds of signals switching in vain. And, thanks to the rendezvous characteristic, things happen when they’re damn good and ready. If something is early or late, it’s ok.

And, lest we overlook the obvious, let’s reinforce the benefit of that last point. While Aloha time tends to get associated with a relaxed, unhurried pace, asynchronous circuits can actually be faster than synchronous ones. If delays are short on a given chip, then everything goes faster because you don’t artificially wait the amount of time you might have to wait on some other slower chip. If the caterer actually shows up early, then the party starts early.

Of course, all of this doesn’t come without a cost. Which is, generally speaking, an area penalty, which can range from 20-50%. Especially when compared to such circuits as multipliers, which have been painstakingly optimized for decades using synchronous techniques. Another contributor to the area is the need for redundant cover logic to ensure hazard-free running.

Debugging and test are also a challenge. You can’t use standard scan-chain technology, since the internal values flying around the system are all marching to their own drumbeats; there’s no good time to sample the system. Tiempo is working on approaches to improving this.

Which is why asynchronous logic isn’t going to replace synchronous logic. There are places where the benefits are well worth the cost. Energy harvesting, for example, can be done in uncontrolled environments – the circuit will work as the conditions change dramatically – and the power consumption – the cost of harvesting the power – will be very low, raising the efficiency of the harvester. The voltage generated may also vary erratically – the asynchronous circuit can tolerate that.

Tiempo also sees benefits at the 22-nm node and below. Large clock trees may be very difficult to manage at that point. Asynchronous means no clock trees. Stay tuned on that one.

So, while it may be a bit disconcerting to leave behind our well-regimented, predictable, orderly, lock-step world in favor of a less tyrannical, more democratic, more individually-accountable domain, relax. Really. Take off those damn black shoes; here are some flip-flops. Way more comfortable. Remove the tie, undo those buttons. Dude… look at those waves. Beautiful.

Yeah, life can be good on Aloha time.

Note *: A similar observation could be made between the Cal and Stanford marching bands. The Cal band is highly regimented, precise, uniform, accurate. Everyone gets (or better get) to their spot at exactly the appointed time. Each note is (or better be) pitch-perfect at the precise moment specified. By contrast, the Stanford band sort of mobs from place to place; they eventually get there, and they eventually play something resembling a song. The benefit is that the Stanford approach is far more tolerant. Of course, with this analogy, it would be too easy for this Cal guy (and one-time band member) to note that the Stanford approach specifically tolerates the less skilled, and that the Cal approach requires more skill at all levels, which would result in the obvious conclusion that the Cal band is better, which is, if true, not the point of this article. So I won’t go there.

More info: Tiempo