Not So Smart About Grids

ADD Triggers a Crash Course on Smart Grids

by Bryon Moyer

After a while, all press releases start to look alike. So I’m not sure what it was that caught my eye, but there it was: “ADD Semiconductor is first technology provider to achieve PRIME official certification.” Maybe it was the fact that some company I didn’t know anything about was the first to be certified on a standard I didn’t know anything about, perverse as that might sound.

I was soon to learn that there were many other things I didn’t know anything about.

A quick look showed that this had to do with smart grids and smart meters. Now, smart meters are something of a hot topic in California, where we’re making the transition from the comfortable old rotating-disk meters to something more modern. And more scary. It’s not happening without a fight. Some people fear the wireless signals. Others don’t trust the power company not to cheat on the billing with the new technology. (Some early billing goof-ups didn’t help matters one bit.)

This further piqued my interest: what does it take for a chip to be compliant with a smart-grid standard?

So I figured, let’s talk to these guys and see what I can learn. Now, they’re in Spain. Yes, there is good technology in Spain, but I have to say, it’s pretty rare that I’m discussing something like this over a connection to the Iberian peninsula.

We got to talking, and it was no time at all before a name got dropped that was very unfamiliar. My notes say, “Ivedrola?”

Now, I ask a lot of “stupid” questions in this job because, most of the time, they’re not stupid. But occasionally they are, and I end up looking like an idiot. Hazard of duty, I guess. But I try to reserve such situations until absolutely necessary, meaning I might wait a bit before exposing my ignorance.

In this case, I quietly did some googling while talking (yeah, I know, I’m too old to multi-task… shhhh… at least I wasn’t driving… or chewing gum…) to see if I could find the answer and act all nonchalant, as if I had known it all along. And, indeed, I found it: Iberdrola. A Spanish power company with which ADD was collaborating.

OK, wait a minute… of all the places to be driving a standard, Spain? I mean, no offense intended, I have nothing against Spain. And, actually, they’re known for some pretty forward-looking ideas on renewable power. (Well, forward-looking if they end up paying off, anyway.) But it just didn’t seem like the concentration of population you might think of as an early market target.

Smart metering ought to be an obvious killer app for a chip maker. Just think of the number of electric meters in the world. How can you miss? And so, with so many thicker population thickets further north in Europe, why start in Spain?

Call me “Grasshopper”: I have much to learn.

Here’s how you can miss: have a dozen or more ways of doing smart metering so that there is no one solution. Almost seems to take the “smart” out of “smart grid.”

Inter-operability for a grid that inter-connects different utilities seems like it would be an obvious smart-grid characteristic. Apparently it’s not. And there are several different technologies used for smart grids.

There are wireless technologies, both ones like Zigbee and full cell-phone technologies like GSM and GPRS. Cell technology in particular can communicate across reasonable distances in less dense areas where things are farther apart. Of course, this also means that the cell carrier enters the picture, complicating the business (and presumably adding cost). Wireless is generally preferred in North America.

But in Europe, with lots of dense cities having lots of close-knit apartment buildings with meters in basements encased in concrete, wireless doesn’t work so well. So they’re going more for the wireline approach.

Here again, though, they’re not all working together. Italy is using Echelon technology, which is also being used in Finland (and elsewhere). France is trying out a number of different wireline approaches to see what to settle on.

PRIME (I’ve seen “PRIME” spelled out as “Powerline Related Intelligent Metering Evolution” and as “PoweRline Intelligent Metering Evolution”) is one of the wireline approaches. It’s intended to provide true inter-operability, with orthogonal frequency division multiplexing (OFDM) signaling at 128 kbps to allow smarter apps to communicate over long runs of wire.

(At least three things I didn’t know anything about in that little paragraph…)

Meanwhile, Asia has its own mix of technologies.

And different power companies in North America are making different choices.

And suddenly this doesn’t seem like quite the killer app you might have imagined.

So how can a new standard and a new technology make inroads? The promise of inter-operability is a nice thing, but how many years has it been that we’ve had non-interoperable cell phone technologies? Inter-operability would be nice there too, but corporate facts on the ground tend to trump nice.

More appealing is cost. ADD in particular is suggesting that their solution is more cost-effective and efficient than competing ones. They’ve combined the MAC and PHY on a single SoC using elaborate DSP algorithms on a 180-nm digital process. This compares to competing 2-chip-plus-analog solutions.

Given the number of meters that need to be installed, low cost – and low power – but mostly low cost – can turn heads.

But assuming that at some point governments will put their feet down and insist on grids that cross borders, ADD is also participating in the OPEN meter project. Their goal is to develop metering standards for all kinds of utilities – electricity, gas, water, and heat – using existing technology standards where possible. Once this effort is complete, they will send it to IEEE to get the coveted IEEE imprimatur.

So, let’s recap. A company I knew nothing about used clever inexpensive technology I knew nothing about that was certified against a standard I knew nothing about so that it could be used by numerous power companies I knew nothing about to compete in a market I knew nothing about against other technologies I knew nothing about.

Good thing I didn’t ask that question about “Ivedrola.” I would have looked stupid.

More info:

ADD Semiconductor

PRIME Alliance

OPEN meter

MIPS Goes Multi-Everything

by Jim Turley

MIPS Technologies gets no respect. The company that practically gave its name to high performance* is running a distant second—a really distant second—to ARM in the 32-bit embedded race. Everybody talks about ARM Cortex-this and Cortex-that, but the fact is that MIPS’s microprocessors are just as good as, and sometimes better than, the ones from its British rival.

A case in point is the company’s new 1074K processor design. The 1074 is a fast, 32-bit CPU design that has an option to go two-way or four-way multiprocessor. (You can do a single-CPU version, too.) It’s fully synthesizable and can run at 1.5GHz in 40nm silicon, even hitting 2.5GHz if you spring for 28nm fabrication.

The 1074K rounds off the MIPS product line, which already includes the 34K, the 74K, and the 1004K. Together, they represent the four corners of the multicore vs. multi-threaded axis. In other words, the 34K is multithreaded but not multicore; the new 1074K is multicore but not multithreaded; the 74K is neither; and the 1004K is both. Confused? So is everyone, and I wouldn’t be surprised if MIPS overhauls its part-numbering scheme before too long.

Despite the missteps in the marketing department, however, MIPS’s engineers have been doing a bang-up job. Internal CPU tweaks have improved the 1074K’s Javascript performance by about 25% over its sibling processor cores, and all four CPU cores remain cache-coherent with a built-in coherence-manager block. The 1074K has variable-sized instruction and data caches, an optional MMU, optional L2 cache controller, and optional floating-point unit.

Perhaps best of all is the 1074K’s low power consumption. It’s a bit daft to measure a soft-core CPU’s power, given that it’s probably only about 5% of the silicon in a finished SoC, but here we go anyway. With caches and FPU enabled, and assuming worst-case timing and temperature, MIPS says the 1074K uses just 0.38mW/MHz/core, or about 0.9W for a dual-core implementation at 1.2GHz. Not bad for a two-headed RISC machine running well in excess of 1GHz.

For comparison’s sake, ARM says its Cortex-A9MPCore consumes 0.31mW/MHz/core, or about 0.5W for a dual-core configuration at full speed. That’s a bit lower than the 1074K’s numbers, but ARM also hand-tunes its designs expressly for low power. In practice, the two cores are probably quite similar.

If you’re interested, MIPS points out that the 1074K CPU is less than one-third the size of Intel’s Atom core. So even if you could put Atom’s x86 CPU in your SoC, you’d likely get less performance, slower clock speed, and much higher power consumption. On the other hand, you’d get to work with Intel and, possibly, Microsoft.

These Might Be the Droids You’re Looking For

MIPS has spent a lot of time and treasure porting Google’s Android operating system to its processors, and it shows. MIPS processors are well-supported by Android, including development kits, sample applications, in-house technical support, and more. MIPS is banking on Android the way PC makers rely on Windows, so they’re going at it with guns blazing. If you’re toying with the idea of developing an Android-based system and you’ve got the wherewithal to develop your own SoC, MIPS processors might be the way to go.

As far as picking your favorite MIPS CPU design, the 1074K makes the most sense if you’re going to use it in dual- or quad-processor configurations. If all you want is a single CPU core, the 74K does that already, and it’s cheaper to license. The 1074K’s cache-coherence manager takes care of gluing the two or four MIPS processors together into a symmetric multiprocessing (SMP) configuration. It snoops the various L1 caches and will launch a speculative read or write to the L2 cache if it detects a cache snoop hit. It even keeps I/O transactions coherent, so that DMAs or intelligent peripherals are kept cache-coherent with main memory.

Anyone considering the 1074K is probably also cross-shopping at the ARM dealership, kicking the tires on the Cortex-A9 MPCore, which also supports two- and four-way clusters. ARM says the A9MP will hit 2.0GHz in TSMC’s 40nm process, but that’s for a hard macro with special libraries, versus MIPS’s fully synthesized vanilla implementation. ARM also quotes typical speeds, while MIPS gives only worst-case numbers. Allowing for a bit of fudging on both sides, I’d say the two CPUs are dead even in terms of clock frequency.

All other things being equal, the ARM Cortex-A9MPCore is probably (depending on workload) slightly faster than the MIPS 1074K at the same frequency, but the latter CPU is smaller in silicon area. Both have a 16-bit code-compression mode, if you’re into that kind of thing. Both have DSP extensions, but only the ARM processor has Java extensions, in the form of Jazelle. On the other hand, MIPS lets you design your own custom instructions, which ARM doesn’t permit.

It’s a tough call. ARM is the more popular CPU family in terms of units shipped and columns of ink printed. It’s also the de facto standard for cellular applications. On the other hand, MIPS is strong in consumer electronics, wired communications, and networking infrastructure. Both have a big healthy third-party software base, especially in their respective market areas. In the end, the decision might come down to which instruction set you prefer, which vendor you prefer, or which application area you’re considering. Toss a coin, and you’ll probably by happy either way.

*Trivia: The MIPS company name originally stood for “microprocessor without interlocked pipeline stages.”

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Click here for more information about Littelfuse SRP1 High-Endurance Solid-State Relays

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