Changing the architecture of electronic systems from parallel I/O to high-speed serial can be challenging. It involves learning a new I/O standard, designing PCBs for gigabit per second differential signals, and applying new debug and verification techniques, to name a few. One way today’s low-cost, low-power FPGAs can help ease these challenges is IP blocks implementing multi-gigabit per second transceiver I/Os (analog and digital circuits) and supporting many popular serial protocols (e.g. PCI Express).  In some FPGAs, such IP blocks are “hardened”, pre-built, and pre-verified blocks implemented on the die, simplifying many tasks for the design team.  

Altera’s Cyclone^® IV GX family, shipping today, provides the industry’s only low-cost, low-power FPGAs with PCI Express hard IP blocks supporting x1, x2 and x4 lane configurations plus end-point and root-port functionality. Furthermore, these PCI-SIG certified FPGAs require only two power supplies for the FPGA core. This results in reduced BOM costs, less PCB space, and a simplified PCB design when compared to other FPGAs needing more power supplies.  

Get started on a new Cyclone IV GX design with the new Altera Cyclone IV GX Transceiver Starter Kit Some key elements in selection of the power solution hinged upon the following criteria: lowest total cost (including inductors, resistors, etc.), high efficiency, low jitter, and small footprint. The following webcast goes into details about the Linear Technology solutions chosen to power the FPGA core, FPGA transceivers, FPGA I/Os and other devices on this $349 FPGA starter kit.

Speakers:  

Jeff Wimett, Technical Marketing, Development Kits, Altera Corporation 

Sharad Khanal, Field Application Engineer – FPGA Systems, Linear Technology