Unterpremstaetten, Austria, April 12, 2010 – austriamicrosystems (SIX: AMS), a leading global designer and manufacturer of high-performance analog ICs, today introduced the AS3900 27 MHz FSK low-power transceiver with built-in star network management, the only one in the 27 MHz ISM band. Operation in this band avoids the interference found in the popular but cluttered 2.4 GHz band and results in a lower amount of energy being absorbed by the human body (SAR) when compared with the 2.4 GHz band — a key consideration for transmitters operated close to the human body.

The AS3900 features austriamicrosystems’ built-in Link manager™ which offers a hardwired, royalty-free easy to use protocol for self-management of all network functions. The Link manager™ simplifies product design and significantly reduces system power compared to alternative approaches requiring protocols that run full-time on an external or internal microcontroller.  Current consumption is only 2.5 uA in polling mode, and typically 3.8 and 4.9 mA in receive and transmit modes respectively, and include the power required to manage the network. 

Mark Richey, Sr. Transceiver Product Marketing Manager, stated, “With the AS3900, austriamicrosystems ushers in a new era of simplicity into the low powered transceiver market space.  No longer do systems design engineers need to consult RF and network protocol experts when integrating low powered networked transceivers into their designs, and time to market for their products is greatly reduced.”

The performance and capabilities of the AS3900 make it well suited for a number of applications where low-power short-range data exchange is required. Such applications include data transfer among devices close to a human body, such as medical and intelligent sporting goods, industrial automation, and any short range sensor network.  While an RF antenna requires size comparable to the wavelength of the operating frequency, the AS3900 operates with a small magnetic loop antenna that resonates at 27 MHz. Besides reducing antenna size, magnetic coupling ensures that the signal travels only a short distance, providing inherently secure communications. The long wavelength at 27 MHz operation allows the AS3900 to provide accurate RSSI (received signal strength indication) signal readings, unlike 2.4 GHz transceivers which suffer from reflection issues that compromise RSSI accuracy.

The AS3900 transmits data at up to 212 Kbit/s and integrates a number of key features, including; a 32.768 kHz crystal oscillator, 24 bits of OTP memory on-chip, battery level detection, wakeup receiver functionality, digital received signal strength indication (RSSI), and a bi-directional serial digital interface (SDI) for simple interfacing.

The AS3900 is available in a 5×5 mm 28-pin QFN package, operates from a 2.2 Volt power supply (functional down to 2.0 Volt), and has an ambient operating temperature range of -40 to +85°C.

Price & Availability

Samples are available now. Pricing in 1,000-piece quantities is less than $3.00.

Technical Support

A demonstration board for the AS3900 is available. Contact austriamicrosystems for price. For further information on the AS3900 or to request samples, please visit www.austriamicrosystems.com/eng/Products/RF-Products-RFID/Transceivers/AS3900

MOUNTAIN VIEW, Calif. — August 9, 2010 — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that TSMC has successfully taped out a complex 28 nanometer (nm) Product Qualification Vehicle (PQV) test chip using Synopsys’ Galaxy(tm) Implementation Platform. Key features used to design the PQV test chip include 28nm design rule support for place-and-route, interconnect process modeling, IEEE 1801-2009 (UPF)-based hierarchical low power flow, power-aware design-for-test (DFT) and advanced signoff capabilities. Synopsys tools exercised by TSMC in the RTL-to-GDSII implementation and signoff flow for this test chip development included DC Ultra(tm) RTL synthesis, IC Compiler physical implementation, PrimeTime(r) SI timing signoff and StarRC™Ultra parasitic extraction.

TSMC’s complex 28nm test chip design consisted of more than 200 million gates of logic and memory combining multiple IP cores and custom designed blocks. The chip’s multiple power and clock domains presented additional design challenges that were efficiently handled by the Galaxy platform tools. TSMC deployed advanced methodologies during the test chip design to address hierarchical power implementation, DFT, advanced routing rules and manufacturability compliance. To address the design’s multiple multi-voltage blocks, TSMC utilised the Galaxy platform’s hierarchical low power flow, including power intent definition described with UPF. This approach enabled the engineering team to implement different sub-blocks of the design concurrently, resulting in faster overall time-to-results. In addition, the Galaxy tools were used to successfully deploy TSMC’s pulsed latch approach to maximise power savings across the chip. To validate 28nm manufacturing compliance, TSMC used Synopsys’ IC Compiler Zroute DFM-aware routing capabilities.

“We continuously work with Synopsys to identify EDA and manufacturing solutions that address the challenges of the latest advanced semiconductor processes,” said ST Juang, senior director of design infrastructure marketing at TSMC. “As a result of our PQV test chip design project, we have successfully used Synopsys’ Galaxy Implementation Platform in our 28nm process, including capabilities for hierarchical low power implementation, routing rules and manufacturing compliance. We appreciate Synopsys’ on-going collaboration during our aggressive process development and deployment projects that allow us to deploy our solutions to our common customers in a very timely manner.”

“As semiconductor process technologies continue to increase in complexity it is essential for industry leaders like TSMC and Synopsys to engage at deep technical levels,” said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. “Through the Galaxy Implementation Platform collaboration with TSMC on its advanced 28nm PQV test chip project, our customers can be assured that the Galaxy Platform can be used successfully in this new technology. This will enable predictable silicon success as they embark on their next design projects.”

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys’ comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 65 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.