SUNNYVALE, CA, May 3, 2010 – MIPS Technologies, Inc. (Nasdaq: MIPS), a leading provider of industry-standard processor architectures and cores for digital consumer, home networking, wireless, communications and business applications, announced today that Mobileye, the global pioneer and leader in vision-based collision prevention systems, licensed its multi-threaded multiprocessing MIPS32® 1004K™ Coherent Processing System (CPS). Mobileye will incorporate the 1004K CPS in its next generation EyeQ™ vision-based SoC for use in driver assistance systems. Mobileye already uses multi-threaded MIPS32 34K™ cores in its current generation EyeQ2™ SoC. Development of the third generation SoC will begin immediately.

According to Ziv Aviram, CEO, Mobileye, “We are having great success using MIPS in our EyeQ2™ product, which has been adopted by several top-tier suppliers and car manufacturers. We are pleased to reaffirm our commitment to MIPS for our next generation product. The EyeQ3™ will be the ultimate driver assistance system for a wide range of vertical markets. With MIPS, we get a winning architecture that provides the reliability, high performance and flexibility needed for automotive applications. MIPS Technologies’ unparalleled service and support will help us get our next generation product to market quickly at the lowest possible cost.”

“Multi-threaded 34K cores helped us achieve a 600% performance gain in the EyeQ2™ over the previous generation, and we are pleased to target even greater performance in the EyeQ3™, with a combination of the 1004K CPS and Mobileye’s innovative Vector Microcode Processors (VMP),” said Elchanan Rushinek, vice president of engineering, Mobileye. “As we did when we selected MIPS cores for the EyeQ2™, we exhaustively benchmarked the new MIPS cores against the competition. We need extreme real-time performance, and we found the 1004K CPS to be a superior solution. With MIPS, our customers can be assured of responsiveness and reliability to help reduce accidents and make roads safer.”

“MIPS Technologies has a strong presence in the automotive market, with significant share in mobile infotainment and a growing presence in the automotive control and advanced driver assistance systems (ADAS) markets. ADAS systems entail advanced applications processing, reliability, and real time response for applications such as collision avoidance and driver safety,” said Michael J. Palma, IDC senior research analyst for consumer semiconductors.

“Leading automotive companies are looking to Mobileye for technologies that not only have the ability to change lives, but save them,” said Art Swift, vice president of marketing, MIPS Technologies. “We are pleased to work closely with Mobileye as it continues to develop advanced driver assistance solutions. The MIPS architecture is a great fit for automotive safety and infotainment applications, and we look forward to expanding our presence in these high-growth sectors of the automotive market.”

Mobileye’s family of EyeQ™ Vision Processors and its broad range of algorithms for mono-camera driver assistance systems target vehicle active safety applications such as lane departure warning, vehicle detection, pedestrian detection, intelligent headlight control and traffic sign recognition.

About the MIPS32 1004K CPS

The 1004K Coherent Processing System (CPS) is the industry’s first multi-threaded multiprocessor IP core. Incorporating multi-threading in each core in a coherent multi-core architecture enables the 1004K multiprocessor to surpass the performance of multi-core systems based on single-threaded processor cores. This performance boost essentially is “free” in both hardware and software, as the additional hardware threads in the cores are minimal in size relative to a typical SoC design, and multi-threading makes use of the same Symmetric Multiprocessing (SMP) versions of operating systems and software programming models as coherent multi-core platforms. Leveraging the multi-threading capability, the 1004K CPS achieves over 2.9 Coremark/MHz per core, putting it among the highest scores available in the database of tested cores on the Coremark.org website. Couple this performance with the small size and low-power implementation, and the 1004K series provides one of the most performance/power efficient solutions in the industry.

About Mobileye N.V.

Mobileye N.V. is headquartered in The Netherlands, with R&D facilities in Israel and offices in the U.S., Cyprus and Japan. Mobileye is a technological leader in the area of advanced image sensing and processing technology for automotive applications, with a product offering covering the entire range of vision applications. Mobileye’s unique monocular vision platform works as a third eye to help drivers improve safety and avoid accidents, and revolutionizes the way we drive. Mobileye’s products containing proprietary software algorithms bundled on the EyeQ™ system-on-chip have been integrated into BMW, GM, Volvo and Yulon Motors (Nissan) models since 2007. For more information, visit:www.mobileye.com.

About MIPS Technologies, Inc.

MIPS Technologies, Inc. (NasdaqGS: MIPS) is a leading provider of industry-standard processor architectures and cores that power some of the world’s most popular products for the home entertainment, communications, networking and portable multimedia markets. These include broadband devices from Linksys, DTVs and digital consumer devices from Sony, DVD recordable devices from Pioneer, digital set-top boxes from Motorola, network routers from Cisco, 32-bit microcontrollers from Microchip Technology and laser printers from Hewlett-Packard. Founded in 1998, MIPS Technologies is headquartered in Sunnyvale, California, with offices worldwide. For more information, contact (408) 530-5000 or visit www.mips.com.

Highlights:
•       Invokes Calibre natively within the Olympus-SoC environment
•       Automatically detects and repairs DRC/DFM violations during implementation
•       Eliminates late stage surprises and unnecessary signoff iterations
•       Improves design quality while reducing time to signoff

WILSONVILLE, Ore., May 3, 2010 – Mentor Graphics Corporation (NASDAQ: MENT) today announced the new Calibre® InRoute design and verification platform, which now enables designers to natively invoke Calibre tools within the Olympus-SoC™ place and route system to achieve true manufacturing closure during physical design. The Calibre InRoute product automatically detects and fixes DRC violations and performs design for manufacturing (DFM) enhancements while optimizing for area, timing, power and signal integrity. The full power of the Olympus-SoC and Calibre platforms together improve design quality, eliminate late-stage surprises, and significantly reduce time to closure.

 “We have used Calibre InRoute on a production 55nm SOC. InRoute has successfully corrected the DRC violations caused by several complex IPs, whose ‘abstract’ views did not fully match the underlying layout, as well as several detailed routing DRC violations,” said Philippe Magarshack, STMicroelectronics Technology R&D Group Vice President and Central CAD and Design Solutions General Manager. “Besides catching manufacturability issues early in the design flow, InRoute allows us to automatically find and repair violations without leaving the Olympus cockpit. This saves engineering time and ensures that no new violations will be created by the fixes. We will take advantage of these unique InRoute capabilities in upcoming 55nm, 40nm and 32nm ST designs.”

“Calibre InRoute with Olympus-SoC is a breakthrough product because it allows our customers to design to tighter margins, realizing higher performance and lower power, while eliminating design-driven manufacturing issues, all without extending time-to-market,” said Joseph Sawicki, Vice President and General Manager for the Design-to-Silicon division at Mentor Graphics. “Calibre InRoute has the potential to be a game changer for design teams already pressed by tight tapeout delivery dates.”

The Manufacturing Closure Problem

Designers are experiencing growing manufacturing closure problems in advanced ICs, such as mismatches between SVRF-based design rules and inaccurate or outdated place and route models; timing and power degradation due to litho, fill and thickness variability; long runtimes due to multiple iterations and huge ASCII file transfers; and lengthy manual repair methodologies. These issues lead to surprises late in the design cycle and delay time-to-market. Existing solutions that simply provide error annotation followed by manual repairs don’t really solve the problem because they are slow, require layout engineers to have deep manufacturing knowledge, and are non-convergent because manual fixes to one problem often create new violations.

The Calibre InRoute Solution

The innovative Calibre InRoute Open Router architecture allows the Olympus-SoC system to natively invoke Calibre SVRF-based DRC and DFM analysis in the inner loop of the router. The Calibre InRoute platform provides interactive, incremental analysis, on-demand GDSII model abstraction, and automated repair techniques targeted at specific DRC and DFM violations. The InRoute platform also performs MCMM-based analysis and optimization during yield improvement modifications to automatically minimize the impact on timing and power.

The InRoute architecture is also extremely scalable—besides the full breadth of DRC, LVS, LFD, CMP thickness variation, CAA and other DFM capabilities in the current Calibre platform, InRoute enables new Calibre rules and features to become immediately available inside the Olympus-SoC design environment as they are added. This ensures the increasing effectiveness of the InRoute platform as DRC and DFM rules get more numerous and complex.

Multimedia is also available at www.mentor.com/calibre-inroute.

About Mentor Graphics

Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $800 million and employs approximately 4,425 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.

SAN JOSE, Calif., May 3 — Xilinx (NASDAQ:XLNX) today introduced the ISE® Design Suite 12 software to enable breakthrough optimizations for power and cost with greater design productivity. For the first time, ISE design tools deliver ‘intelligent’ clock-gating technology that reduces dynamic power consumption by as much as 30 percent. The new suite also provides advances in timing-driven design preservation, AMBA 4 AXI4-compliant IP support for plug-and-play design, and an intuitive design flow with fourth-generation partial reconfiguration capabilities that lowers system cost for a broad range of high performance applications.

With full production support for all Xilinx® Virtex®-6 and Spartan®-6 FPGA families, the ISE 12 release continues its evolution as the industry’s only domain-specific design suite with interoperable design flows and tool configurations for logic, digital signal processing (DSP), embedded processing, and system-level design. In addition, Xilinx incorporated a number of software infrastructure and methodology enhancements that improve run time, streamline system integration, and expand IP interoperability across its latest generation device families and Targeted Design Platforms.

“Xilinx FPGAs are the innovation platform for tens of thousands of designers across a wide range of applications and markets. Designers continue to adopt our FPGAs for their next generation products, because they can balance the demands for reduced power and high performance with lower system costs,” said Tom Feist, senior marketing director for ISE Design Suite at Xilinx. “ISE 12 design suite is optimized for these goals with power and cost-saving software innovations that maximize the capabilities of Virtex-6 and Spartan-6 devices and platforms and increase overall design productivity.”

Intelligent Automation for Power Optimization

ISE Design Suite 12 introduces the FPGA industry’s first intelligent clock-gating technology with fully automated analysis and fine-grain (logic slice) optimization capabilities specifically developed to reduce the number of transitions, a primary contributing factor of dynamic power dissipation in digital designs. The technology works by analyzing designs using a series of unique algorithms to detect sequential elements (‘transitions’) within each FPGA logic slice that do not change downstream logic and interconnect when toggled. The software generates clock-enable logic that automatically shuts down the unnecessary activity at the logic slice level to accumulate power savings without having to shut off an entire clock network.

Greater Productivity, Better Performance

Advanced design preservation capabilities in the ISE 12 design suite enable designers to reach design closure fast with repeatable timing results. Designers can partition designs to focus on achieving required timing for critical blocks, and lock those blocks to preserve placement and routing while they work on the rest of the design. To foster plug-and-play FPGA design, Xilinx is standardizing IP interfaces on the open ABMA® 4 AXI(TM)4 interconnect protocol, which eases integration of IP from Xilinx and third party providers and maximizes system performance. Xilinx also worked with ARM to define the AXI4, AXI4-Lite, and AXI4-Stream specifications for efficient mapping into its FPGA architectures.

Partial Reconfiguration Lowers Cost

“Partial reconfiguration is great for space applications. Not only does it make on-orbit ‘upgrades’ possible, but it also drastically reduces the rad-hard, non-volatile memory requirement, which is expensive and not very dense,” said Jonathon Donaldson, an embedded systems engineer at Sandia National Laboratories. “We’ve been using partial reconfiguration technologies since their inception with Xilinx FPGAs, and are pleased with the quality progression of the tools. The tools have reached the point where they are practical to use in almost any case, and are now even easier with the newest version of the ISE Design Suite.”

Partial reconfiguration technology allows the dynamic modification of FPGA logic blocks by downloading partial bit files without interrupting the operation of the remaining logic. ISE Design Suite 12 makes this technology easy to use with Xilinx FPGAs by providing an intuitive interface and simplified methodology that closely aligns with the standard ISE design flow with which users are familiar. The ISE partial reconfiguration flow now uses the same proven Xilinx tools and techniques for timing closure, design management and floorplanning, and design preservation.

Support for fourth generation ‘on-the-fly’ partial reconfiguration technology enables designers to dramatically reduce system cost and power consumption by fitting sophisticated applications into the smallest possible device. Developers of next-generation wired Optical Transport Network (OTN) solutions can implement a 40G multi-port muxponder interface with one-third fewer resources as compared to devices without partial reconfiguration (see March 16, 2010 news release). Many other applications including software-defined radio also benefit from the increased flexibility provided by on-demand reconfiguration with Xilinx FPGAs.

Start Designing Today

ISE Design Suite 12 innovations will rollout in phases with intelligent clock gating for Virtex-6 FPGA designs shipping now with the 12.1 release, partial reconfiguration for Virtex-6 FPGA designs starting in the 12.2 release, and AXI4 IP support to follow in the 12.3 release. The ISE 12 suite works with the latest simulation and synthesis software from Aldec, Cadence Design Systems, Mentor Graphics, and Synopsys.

Additionally, the 12.1 software features an average of 2X faster logic synthesis and 1.3X faster implementation run times for large designs than previous versions and an improved embedded design methodology. It also includes an expanded offering of production qualified IP for the Virtex-6 FPGA Multi-mode Radio Targeted Design Platform, Spartan-6 FPGA Industrial Automation and Industrial Imaging Targeted Design Platforms, as well as the Virtex-6 HXT FPGA 100G OTN and Packet Processing Targeted Design Platform that will be available later this year.

Availability & Pricing

ISE Design Suite 12.1 is immediately available for all ISE Editions and list priced starting at US$2,995 for the Logic Edition. Customers can download full-featured 30-day evaluation versions at no charge from the Xilinx web site. To get started today with the 12.1 software release or for more information about the power and cost-saving design methodologies and productivity innovations introduced in ISE Design Suite 12, visit: www.xilinx.com/tools/designtools.htm.

About Xilinx

Xilinx is the world’s leading provider of programmable platforms. For more information, visit www.xilinx.com.