The applications space for the PCI Express standard continues to expand tremendously as it becomes more commonplace in PCs and other systems where inexpensive, high-speed interconnect is required.  In order to meet the demands of this growth, a plethora of systems solutions intended to get designers up and running quickly with PCI Express have been developed by a growing number of hardware and software vendors.  As a result, designers often are faced with a bewildering number of choices when creating and implementing PCI Express-based add-in cards or systems.  These choices include the width of the PCI Express link, the number of virtual channels, which topology to support, whether to use an IP (intellectual property) core and which device(s) to choose for implementation, among many other decisions.

PCI Express Device Implementation Decisions

Regarding PCI Express device implementation, designers must make a number of decisions as well, such as whether to use an ASIC, an off-the-shelf ASSP, an ASSP with an external FPGA for logic, a SERDES-based FPGA or a standard FPGA with an external PHY chip.  The device decision is usually tempered by several key factors:  cost, volume, form-factor and flexibility. 

ASICs have been the device of choice for PCI Express-based systems when volume is expected to reach millions of units per year (or over the product’s lifetime), such as graphics processors for add-in cards or PC motherboards.  ASICs offer the most flexibility for power optimization, packaging and volume cost reduction, but come with prohibitive up-front, non-recurring engineering expenses (NRE).  Especially for state-of-the-art 65 and 90 nanometer technology, ASICs present a formidable barrier to entry for many PCI Express OEMs (original equipment manufacturers), except for those large OEMs who are willing to risk their R&D budget on expensive ASIC respins.

For small- to mid-volume production, (i.e. up to the lower end of hundreds of thousands of units) PCI Express ASSPs have been a popular choice for designs, especially when there is either no additional value-added logic, or the logic is small enough that it can be relegated to a small external standard FPGA.  However, it is fairly common for most PCI Express OEMs to add significant, value-added “secret sauce” to their designs.  To this end, FPGA vendors have jumped into the fray to present a third alternative to cost-prohibitive ASICs or functionally limited ASSPs.  Because the tradeoffs and compromises between FPGAs and ASICs, particularly for small to mid-volume production designs (the volume of many PCI Express OEMs), are already well understood, they are not addressed in this article.  Instead, the focus is on small- to mid-volume production systems where either ASSPs or FPGAs may be considered as a design solution.

Until recently, designers considering the tradeoffs between PCI Express ASSPs and FPGAs have had somewhat limited choices.  A number of general-purpose PCI Express chips have been available from commercial vendors such as IDT, Pericom and PLX.  Alternatively, traditional leading FPGA vendors have offered either standard FPGAs with external PHY support or high-end SERDES-based FPGAs with embedded PHY support for PCI Express.

Unfortunately, none of these have been optimum choices, for several reasons.

While PCI Express ASSPs have the advantage of being single-chip solutions and are available in small-scale packaging, they have the disadvantage of limited configurability and hard-coded compliance to a given PCI Express standard specification (e.g. 1.0a, 1.1).  Furthermore, if additional logic is required, it must be implemented outside the ASSP in an external (non SERDES-based) FPGA.  The combination of an ASSP with an external CPLD or FPGA is unattractive for obvious reasons –increased real estate and power, as well as the additional cost of a two-chip solution. 

For similar reasons, the combination of standard FPGAs (with an embedded PCI Express soft IP core) and an external PHY chip is no more desirable than the combination of ASSPs with CPLDs/FPGAs.  However, in fairness, there is one advantage in that the FPGA can accommodate new features or enhancements to the PCI Express IP controller core implemented within.

Finally, traditional high-end SERDES-based FPGAs with embedded PCI Express PHY support offer a single-chip solution similar to ASSPs, with the bonus of FPGA fabric look-up-tables (LUTs) for customization.  Drawbacks, however, include high power consumption and an overabundance of device resources and features, which increases design complexity.  Furthermore, for small to medium volume PCI Express designs, they can be prohibitively expensive on a per-piece basis compared to either ASSPs or ASICs.

Best of Both Worlds

Manufacturers of virtually every small-to-medium volume PCI Express-based system – such as broadcast or audio production equipment, industrial control systems, medical imaging, video capture/acquisition and video surveillance – wish to implement their own logic design in a PCI Express-based system in order to create competitive, value-added differentiation.  In addition to creating their own secret sauce, OEMs designing PCI Express systems usually prefer single-chip solutions, built-in PHY/SERDES support, an easy-to-learn/use device feature set, flexible topology, small footprint packaging, low power, the capability to upgrade features and the ability, with minimal penalty, to migrate to new versions of the PCI Express specifications as they evolve. 

Also, because their applications tend to be cost-sensitive, these manufacturers also are seeking relief from the price premium of traditional SERDES-based FPGAs.  In other words, PCI Express designers want the best capabilities of both ASSPs and FPGAs combined in one device.  Figure 1 illustrates the advantages and disadvantages of each of several solutions available in terms of flexibility, integration and cost.  As shown in the diagram, for PCI Express design both ASICs and ASSPs can offer per-piece cost advantages, but are limited in both flexibility and system integration.  The ASSP/FPGA and FPGA/PHY combinations offer more flexibility and system integration capabilities, but come with real estate, power and cost penalties.  For small to medium volume designs, new second-generation low-cost FPGAs with embedded PHY can offer the optimal combination of system integration and flexibility, with pricing that is competitive with ASSPs.

Fig. 1 Tradeoffs in Price, Flexibility, and System Integration among ASSP, ASIC, ASSP + FPGA, FPGA + PHY, and FPGA with PHY Solutions

FPGAs such as the low-cost LatticeECP2M device family address the requirements of small- to mid-volume OEMs by offering a hybrid ASSP/FPGA capability in a single device.  For example, like a PCI Express ASSP, the LatticeECP2M device offers 3.125 Gbps SERDES with an embedded Physical Coding Sublayer (PCS) that supports the PCI Express PHY layer (Figure 2), but with the transaction layer and data link layers implemented in soft IP.  Also included are a streamlined low-cost FPGA fabric, advanced DSP blocks, a healthy amount of block memory (up to 5.3 Mbits) and a range of FPGA LUT counts and SERDES channels to choose from, all wrapped up in small footprint packaging with low power consumption.  Because this particular device family is available with pre-verified and PCI-SIG v1.1-compliant PCI Express IP x1 and x4 soft IP cores, implementation is straightforward.  This solution enables OEMs to add their secret sauce and evolve with the PCI Express specification over time and within the same device.

Fig. 2 LatticeECP2M PCI Express Protocol Support including PHY Layer

Comparing Solutions

A simple but typical design example involving a video frame grabber board, which is used in manufacturing and security/surveillance applications, illustrates the value proposition of a second-generation SERDES-based FPGA solution versus an ASSP-based solution.  In this example (Figure 3, left), an ASSP is used as a PCI Express x4 endpoint controller.  Multiple digital still frames that have been captured via a Camera Link interface have been processed by a separate FPGA (approximately 50,000 LUTs) and then passed over to the PCI Express ASSP for transfer to system memory or to a display.  In this particular case, the OEM’s functionality is implemented in a separate standard FPGA (without SERDES) that performs various image-processing tasks such as scaling, contrast/brightness control and formatting.  The value of the ASSP is its PCI Express controller functionality and PHY support, while the OEM’s secret sauce is contained within the separate FPGA.  Depending on the manufacturer, the features included, and the purchasing channel, a PCI Express-based video frame grabber board may resale from about $700-$1,500.  The resale combination of the ASSP and the FPGA on the board in 1,000 to 10,000 unit quantities is roughly around $50-$70.

Fig. 3 Board Real Estate, Power, and Cost Optimization of a PCI Express Video Frame Grabber Board

A traditional high-end SERDES-based FPGA from one of the two leading FPGA vendors certainly could encapsulate both the PCI Express x4 controller as well as the OEM’s value-added design.  Assuming this scenario, in 1,000 to 10,000 unit production quantities, there are high-end SERDES FPGAs ranging from approximately 30,000 to 60,000 LUTs that could easily command a resale price from $400 to $1,000, which would be unacceptable in a low-cost board such as a video frame grabber.

Converting the design to a low-cost SERDES-based FPGA yields all the benefits of the high-end FPGA, but without the substantial cost penalty.  For example, a LatticeECP2M FPGA-based solution with SERDES and PCI Express PHY support (Figure 3, right) provides the same functionality as the high-end FPGA, but with small to mid-volume pricing comfortably within the same range as the ASSP/standard FPGA combination.  In fact, depending on the specific device chosen and the amount of FPGA logic required for the OEM’s value-added design, it is entirely possible for the low-cost SERDES-based FPGA device to not only come in with a lower resale than the ASSP/standard FPGA combination, but to approach that of the ASSP itself.

Benefits of the Low-Cost SERDES-Based FPGA Solution

 Along with economic advantages come several benefits compared to the ASSP/FPGA solution.  First, the most obvious benefits are reduced board real estate, power and cost.  Especially if the application is form-factor-, power- and cost-constrained like a broadband ExpressCard, this can be a tremendous advantage for a low-cost SERDES-based FPGA solution.  The second benefit is improved timing and testability of the overall solution, since the OEM’s value-added logic can be located within the same device as the PCI Express controller.

A third benefit is the hallmark of FPGA technology – flexibility.  If the PCI Express link width is running at the 2.5 GT/s rate, the Lattice solution, for example, enables the OEM to easily migrate from PCI Express 1.1 specifications to the 2.0 specifications using the same board design.  The reason this is possible is that, from an electrical point of view, PCI Express version 1.1 and 2.0 are identical at the 2.5 GT/s rate.  The IP would only need an update for the transaction, data link, and physical layers in order to accommodate several new 2.0 features such as automatic link width and speed negotiation, but this is readily achievable since customers can easily upgrade to the newer specification via a simple IP upgrade.

Furthermore, as mentioned earlier, PCI Express ASSPs are hard-wired to a given specification.  An OEM wishing to transition from PCI Express version 1.1 to 2.0 must purchase a new ASSP and change the board design in order to accommodate the new specifications.  The flexibility of the FPGA enables the OEM to extend the life of the board and future-proof it for the market transition to the PCI Express version 2.0 specifications when other hardware OEMs begin to offer 2.0-compliant systems. 

Summary

When compared to ASICs, FPGAs have always had several compelling and well-known advantages for OEMs with small to mid-size production requirements.  With respect to ASSPs, FPGAs have historically not been able to offer much of an advantage, especially in terms of cost.  However, the advent of second-generation, low-cost SERDES-based FPGAs, such as the LatticeECP2M family, which merge a low-cost FPGA fabric with high-end PHY support for PCI Express and other high-speed interfaces, has created a unique opportunity for FPGAs to compete effectively against PCI Express ASSPs.  By focusing on the explosive growth of the PCI Express market with such solutions, low-cost SERDES-based FPGAs are poised to take market share away from ASSPs.

About the Author: Alex Gargarita is an Intellectual Property (IP) Marketing Manager at Lattice Semiconductor Corporation.  He has over 19 years experience in both the semiconductor and software industries.  Prior to joining Lattice, Alex spent eight years in various FPGA marketing positions, including sales and marketing management for an FPGA software start-up.  He also has held senior EDA marketing positions at Mentor Graphics and Synopsys, where he managed strategy for FPGA synthesis software product lines.  Alex has a BSEE degree from Santa Clara University.