Of course analog engineers themselves had a different view. Increasingly they saw EDA tools bring automation to digital circuit design, particularly in layout. They, on the other hand, still had to design by hand and by intellect, since they were dealing with much more complex issues than a stream of zeroes and ones, highs and lows. And, unlike for digital, there was only a handful of universities providing training in analog technologies.

Sometime at the end of the twentieth century, things started to change. Suddenly analog and mixed signal started getting above itself. Handheld consumer devices, like phones, needed lashings of analog, and the economics of manufacturing meant that it could no longer be kept at a distance on a separate chip and converted neatly for digital processing, but, horror of horrors, it would have to be combined with digital on the same chip. This presents a whole range of problems, some of which we will look at later, but the overarching question is: “Is this a new Golden Age for analog?”

The idea was first floated for me at lunch at National Semiconductor just before ESC this year. I was listening to two mature Nat Semi analog designers discussing a range of issues, when David Anderson said, “This is a new golden age for analog.” Bob Pease, veteran analog warrior, mountain trekker, VW Beetle enthusiast, and occasional curmudgeon, growled that analog had never gone away, but after a few more minutes’ conversation conceded that things were looking up.

Over the next few months, there were other straws in the wind. I knew that in 2007 IP provider MIPS had bought Chipidea, the Portugal based leader in analog IP, and was preparing platform designs integrating analog elements with MIPS processor cores. STMicroelectronics was reported as saying that it was now concentrating on analog — in fact, returning to its roots. ST also announced a joint-venture in wireless with NXP. Silicon Labs acquired Integration Associates, an analog specialist. Voracious acquirer On Semi added Catalyst, another analog house, to its portfolio. So companies are seeing analog as important. It looks as though it could be a good time to be an analog engineer.

But that brings up the first question. Where are these analog engineers coming from? According to Bob Pease, Nat Semi is always looking for good analog designers, and it takes them from wherever it can find them: one of their best designers was previously a TV repairman in Tehran. The company recruits technicians from the College of San Mateo, a two year college, and trains them up to become designers. But they are always looking for new recruits.

Carlos Leme, who is CTO of MIPS Technologies’ Analog Business Group, previously Chipidea, says that they also provide in-house training. They recruit electronics graduates and train them to become analog engineers in their Portugal facility. Even though Leme says that analog design is becoming less of an art than it used to be (and almost all the analog people I spoke to feel that solving problems in analog design requires high levels of creativity), he feels that, despite the development and consolidation of design methods, an analog designer has to master many different techniques.

Nat Semi, MIPS and other companies are having to invest heavily in training because universities in Europe and the US are not providing electronics degree courses with high analog content, or even much analog content at all. As we discussed only a few weeks ago (Fame Academy for Engineers) there are severe issues with the supply of electronics engineers generally: the position with analog engineers is much worse. That is, presumably, at least part of the reason behind TI’s sponsorship of an analog design prize for students, announced earlier this year: by attracting students with a significant prize, they hope to make the challenges and satisfactions of analog design better known.

And the lack of engineers is exacerbated by a lack of tools for automating the design process: there are far fewer design tools available for analog than there are for digital. This reflects partly the relative importance that has historically been placed on digital and partly what analog engineers claim is the greater complexity of their design process. Gary Smith EDA, the market research company, has been looking at the landscape of analog design tools. In a briefing note, Chief Analyst Mary Anne Olson wrote, “… the [design] process is still predominantly manual, and most of the older tools are insufficient for designs below 90nm.” The time taken to carry out physical design is measured in weeks to months, where for digital devices it is measured in hours to days to weeks.

A further complication is that analog designs do not scale in the same way as digital designs: while a 90nm digital design may require little work to be retargeted at 65nm, an analog design has to be completely re-built, according to Leme of MIPS, particularly since different process nodes are associated with different power supply voltages. And while today digital designs in 45nm are building high volumes, analog designers are finding it hard work to transition to 65nm, with a significant part of volume manufacturing still at 130nm.

Olson sees the analog EDA market as being a huge opportunity for new entries with innovative technology. Gary Smith EDA, for which she works, has figures that show that the sales of digital EDA products are roughly ten times those of analog.

Perhaps as the SoC design teams increasingly find their project schedules handicapped by integrating analog areas in their design, the investment in research and new companies will be forthcoming to create these tools.

But the alternative to designing from scratch, and a solution that is already widely used in the SoC/ASIC world, is to use IP. And Leme clearly feels that it is the right option for many applications. (Well, since that is what his company does, he would, wouldn’t he? But the argument does have a great deal of force.) But adding analog IP to a digital design is not always easy: some claim that it is another example of aspects of analog being just as much an art as a science. So while MIPS offers select blocks of IP, the company is also developing platform solutions, where an engineer implementing an SoC/ASIC effectively drops a complete solution, for example a touch screen interface, without having to know anything about the analog issues involved. Even the standard IP blocks are designed to be as self-contained as possible and are supplied with Verilog models for verification.

Since MIPS, as Chipidea, has been around for a while (over ten years), it has built a pretty large bank of designs and developed the expertise needed for retargeting/redesigning products for new process modes, vital if the analog IP is to keep step with the digital circuits on an SoC. They are currently designing at 45nm, and while this is behind the leading edge of process technologies, it is still alongside the volume products.

Digitally enhanced analog is a technique that is being developed to cope with the way analog performance falls off at process modes beyond 90nm. It uses digital circuitry to calibrate the analog and provide feedback to the analog front end – moving analog into a new area of mixed signal.

So, back to our first question: “Is this a new Golden Age for analog?” It certainly has the opportunity to be so. A final straw in the wind is the list from analysts at Future Horizons of the ten fastest growing semiconductor applications in the next five years. Seven applications are predicted to be wireless based, which by definition requires analog, and the other three also include strong elements of analog. What might limit this opportunity could be the lack of engineers to design the analog circuits and the tools to make these engineers productive. So the golden age holds out golden prospects to both engineers and to those creating design automation tools.