Today’s high-capacity and high-performance FPGA designs are becoming more complex and require more third-party intellectual property (IP) cores. These hard IP blocks include pecialized high-speed multi-gigabit transceiver (MGT) I/O cores, PCI Express cores, clock management modules, FIFOs and complex processor cores, such as the PPC440 in the Virtex5 device. The DSP clock management cores (DCMs), BlockRAMs, and FIFO models are in a class of Hard IP cores provided in standard libraries because the simulation models do not require source code protection. However, the other class of Hard IP cores, which includes MGT I/O cores, PCI Express, TEMAC, and PPC440 cores, requires that the simulation source files be protected. Until now this last set of hard IP models was provided to customers as SmartModels, which have support limitations, and ease-of-use and performance issues. Recent developments in the HDL language standards and support for these new standards by simulation tool providers now allow Xilinx to provide hard IP models for the Virtex-5 Family of Platform FPGAs using SecureIP libraries instead of SmartModels. SecureIP models provide FPGA designers with significant ease of use and performance advantages over SmartModels.
The following sections provide an overview of Hard IP support issues in FPGA devices and benchmark results that compare Secure IP models with SmartModels.
The Issues with Supporting Hard IPs in FPGA Devices
When the simulation model source code requires protection, Xilinx provides designers with SmartModels for simulation of complex Hard IPs that are embedded in FPGA devices. SmartModels have performance issues, ease-of-use issues, and platform limitations when used by designers. These models run more slowly than RTL behavioral code because the simulation tools require a more complex communication interface (called SWIFT) and sets limits on the simulator optimization compared to using just behavioral RTL code. Because a lot of development time is spent in functional simulation, it is more difficult to debug issues when using SmartModels because the behavioral RTL code is the primary focus.
The Secure IP encryption methodology recently added to the Verilog Language Reference Manual (LRM) as an IEEE standard enables IP providers to support models that offer the advantages of fast RTL simulation run times without the performance limitations of SmartModels. The encrypted library models are referenced and compiled by the customer with a given simulation vendor’s software release and are used the same way as other non-encrypted library models and in a manner completely transparent to the FPGA designer. Encrypted library models provide customers with Verilog RTL behavioral models that are fully optimized by simulation tools to provide the fastest possible simulation run times and also provide protection for the underlying simulation model source code.
The Verilog Secure IP Encryption Methodology
The Verilog encryption standard is defined and published in the IEEE STD 1364-2005 version of the Verilog LRM. Using this encryption standard has allowed Xilinx to work with simulation partners to provide hard IP models in libraries that look and compile in the same way as standard libraries used by customers with their simulation tools. The Secure IP libraries appear transparent to the end user and are referenced and used in the same way as standard libraries. However, Secure IP libraries are distributed differently and work differently than standard libraries. Secure IP models are distributed as encrypted files, usually named with a .vp extension. A Secure IP model may have one or more encrypted files and these files can only be decrypted by using a key. To use a Secure IP model within a simulator (or other software tool) that simulation software tool must use a key to decrypt the model, compile it, and then set up an equivalent binary file to use with that simulator. For a customer who uses a licensed version of a simulator tool that supports Secure IP libraries provided by Xilinx, this is completely transparent. The customer compiles the Secure IP libraries, and the supported simulator performs the needed decryption when the libraries are compiled with a version that supports encryption. From this point on, the customer references the Secure IP library as a standard compiled library, and the simulator uses the library reference as it does with other standard libraries. When customers run simulation using a Secure IP model, it looks like a black box in that they can view or monitor only signals that the IP provider specifies. Secure IP models provide the same equivalent signal visibility as SmartModels, but only allow users to view or monitor signals in a simulation tool as specified in the model by the IP provider.
Set Up and Use of the Secure IP Models in the Xilinx Design Flow
The Secure IP models are distributed as a set of encrypted files (with .vp file extensions) and are included in a zip file within the ISE Design Suite, release 10.1 library directory. After users install the ISE design tools, they must run the compxlib program, which will compile and set up the Secure IP library, along with the other standard simulation libraries in the ISE 10.1 release for use in a supported simulation tool. The Secure IP libraries are supported in ModelSim® 6.3c and later software releases. Because Secure IP models are only supported in Verilog, customers using these models in a VHDL design must have a mixed-language license to use them. Support for Secure IP models NCSIM from Cadence and VCS from Synopsys is scheduled for the next release of ISE.
When compxlib is run, the encrypted models within the Secure IP library are compiled and set up along with the standard libraries. The compiled Secure IP library is set up in a new library directory named secureip, which is placed in the same area as the other standard compiled libraries, according to users’ specifications when they run the compxlib program. Compxlib also creates a modelsim.ini file, which contains a reference to the Secure IP library that is similar to the UNISIM and SIMPRIM libraries. From this point, the user uses the modelsim.ini file to reference the SecureIP libraries in exactly the same way as the other standard libraries.
Because the SecureIP libraries are made up of RTL source code, which is compiled and used like other standard libraries, no special environmental variables are required to use them. When the simulator tool optimizes RTL source code in a standard library, it also optimizes the secure IP libraries and provides the same performance advantages. This allows Secure IP libraries to provide significant performance advantages over SmartModel, as mentioned above. The following diagram shows the required references and interface for SmartModels compared to that of Secure IP library models.
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Figure 1: An overview of SmartModel Use
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Figure 2: An overview of SecureIP Model Use
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Benchmark Results Comparing SecureIP Models to SmartModels
The following section summarizes the benchmark results that compare Secure IP models to SmartModels using ModelSim 6.3e with the ISE 10.1 release (Service Pack 1). ModelSim is the only simulator that formally supports the Secure IP models in ISE 10.1 release, so only these results are presented here.
The benchmarks compare the simulation performance measured by running a set of designs that use one or more hard IP models as a Secure IP model versus using the equivalent SmartModel in ModelSim. The benchmarks were made up of a set of design cases that instantiate a specific hard IP model along with a set of customer designs that instantiate one or more Hard IP models from the Virtex5 FPGA UNISIM library. The hard IP models include the GTP_DUAL, GTX_DUAL, TEMAC, and the PCI_EP.
The ISE 10.1.01 release (Service Pack 1) libraries were compiled and both versions of a design were run in ModelSim 6.3e using the default (vopt mode) with optimization switched on. The benchmark designs were run on a 64 bit Linux machine using Red Hat Enterprise Edition 4.0 using the 32 bit executables of ModelSim, which is recommended by Mentor Graphics®.
The simulation performance improvement using the Secure IP models averaged 247%, or about a 3.5X simulation speed improvement, compared to using SmartModels. The performance run time improvement using SecureIP models compared to SmartModels, which included compilation time, load time, and simulation time, averaged 166%, or about a 2.7X performance improvement.
The following table lists a comparison of the improvements with Secure IP models in the ISE 10.1 release and the ModelSim 6.3e release, compared to SmartModels.
| Average percentage simulation improvement |
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Average speed up factor (total compile.load and simulation run time) | |
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247%
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166%
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2.7X
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Table 1 SecureIP models significantly out performs SmartModels on all fronts |
Improved Simulation Performance Using Models in Fast Simulation Mode
Another area of focus for improving simulation performance is with a specific class of models that can be run in FAST simulation mode. Several Virtex5 FPGA primitives in the ISE 10.1 release have this feature. These include the BlockRAMs, FIFO, and DSP48E blocks. These models are only included in the Verilog library and VHDL UNISIM library. For more details on these primitives, refer to the ISE 10.1Libraries Guides.
These models can be run in two modes, according to what is set in the SIM_MODE parameter. The SIM_MODE parameter can either be set to SAFE, which is the default for using the model in legacy mode, or FAST to run the model in a configuration optimized to improve simulation run-time performance. When the model is simulated in SAFE mode, the behavior is guaranteed to match the behavior seen in the hardware. The simulation shows all the issues that may occur if the model encounters problems or corner case conditions. When the model is run in FAST mode, certain checks or conditions are not flagged. The conditions that are not checked or flagged depend on the model. Refer to the ISE 10.1 Synthesis and Simulation Design Guide under reducing simulation runtimes for more details.
In the ISE 10.1 release, the DSP48E model was changed so that performance improvements will also be seen when this model is run in SAFE mode which maintains the same functionality checks that exist with the legacy model. Some additional performance improvements to the model can be realized in FAST mode. For the BRAM and FIFO models, performance improvements will only be seen when the model was used in FAST mode. Because some of the model features used in SAFE mode provide important checks and safeguards, the user must understand the trade offs in using the model in a configuration that is optimized for performance.
Before using models in FAST mode it is recommended that designers use the simulator profiler on their design to determine which components or models in their design have the most impact on performance. If the designers determine that some of the components in their design that have the most impact on performance can be run in FAST mode, they will be able to make some improvement in performance using these in their design. The performance results seen using models in FAST mode in a typical design will depend on the size of the design, how many models are being used in FAST mode, and, what other components are used in a design. Using models with different simulation modes is supported in all Xilinx-supported simulators. The example below shows a section of Verilog source code that instantiates a Virtex-5 FPGA DPS48E model, which is in the UNISIM library. The SIM_MODE parameter must be set to FAST for each instantiated instance where the user wants to use the model in fast mode.
module DSP48E_ADDSUB ( A, B, C, CLK, ALUMODE1, ALUMODE2, SUM);
//Inputs
input [29:0] A;
input [17:0] B;
input [47:0] C;
input CLK;
input [3:0] ALUMODE1;
input [3:0] ALUMODE2;
//Outputs
output [95:0] SUM;
wire [47:0] c_reg;
wire [47:0] sum_reg;
wire carrycascout;
/////////////////////////////////////////////////////////////////////
// Instantiation of DSP48E named as utt_0 //
/////////////////////////////////////////////////////////////////////
DSP48E #(.SIM_MODE(”FAST”)) //Specify in line parameter for FAST mode
utt_0 (.CARRYCASCOUT (carrycascout),
.P (sum_reg),
.A (A),
.ACIN (30’b0),
.ALUMODE (ALUMODE1),
.B (B),
.BCIN (18’b0),
.C (C),
.CARRYCASCIN (1’b0),
.CARRYIN (1’b0),
.CARRYINSEL (3’b0),
.CEA1 (1’b1),
.CEA2 (1’b1),
.CEALUMODE (1’b1),
.CEB1 (1’b1),
.CEB2 (1’b1),
.CEC (1’b1),
.CECARRYIN (1’b1),
.CECTRL (1’b1),
.CEM (1’b1),
.CEMULTCARRYIN (1’b1),
.CEP (1’b1),
.CLK (CLK),
.MULTSIGNIN (1’b0),
.OPMODE (7’b0110011),
.PCIN (48’b0),
.RSTA (1’b0),
.RSTALLCARRYIN (1’b0),
.RSTALUMODE (1’b0),
.RSTB (1’b0),
.RSTC (1’b0),
.RSTCTRL (1’b0),
.RSTM (1’b0),
.RSTP (1’b0) );
…
…
Below are the benchmark results that measured simulation run times on several Virtex-5 FPGA library components using the FAST simulation mode in ModelSim, NCSIM, and VCS. The design cases used are specific to measuring the simulation performance improvement of each model in the ISE 10.1 release that has FAST mode compared to the original, or legacy model, from the ISE 9.2i release and is not a typical customer design. The design cases were run on a 64 bit Linux machine with Red Hat Enterprise Edition 4.0 using the 32 bit executables of each simulator. The improvement seen varied with each simulator, although the average improvement for the FAST version of the RAM models was over 2X faster for NCSIM and VCS. The FAST DSP48E and FIFO models showed performance improvements up to 37% or 1.4X , and 25% or 1.25X respectively on ModelSim and VCS. These initial results represent the first version of model improvements. The performance results seen using models in FAST mode in a typical design vary based on various conditions previously mentioned. Work is continuing at Xilinx and with our simulation partners to provide additional improvements in future releases.
| DSP48E Component Simulated in FAST Mode in the ISE 10.1 Release Compared to Legacy Model in the ISE 9.2i Release |
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Simulator and version
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Average percentage simulation run time improvement
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Average speed up factor on simulation run times
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ModelSim 6.3c
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37%
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1.4X
|
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NCSIM 6.1
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37%
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1.4X
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VCS 2006.06-SP1
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24%
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1.24X
|
| RAMB18SDP Component Simulated in FAST Mode in the ISE 10.1 Release Compared to Legacy Model in the ISE 9.2i Release |
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Simulator and version
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Average percentage simulation run time improvement
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Average speed up factor on simulation run times
|
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ModelSim 6.3c
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88%
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1.9X
|
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NCSIM 6.1
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150%
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2.5X
|
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VCS 2006.06-SP1
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92%
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1.92X
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| RAMB36 Component Simulated in FAST Mode in the ISE 10.1 Release Compared to Legacy Model in the ISE 9.2i Release |
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Simulator and version
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Average percentage simulation run time improvement
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Average speed up factor on simulation run times
|
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ModelSim 6.3c
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83%
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1.83X
|
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NCSIM 6.1
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104%
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2.04X
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VCS 2006.06-SP1
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101%
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2.01X
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| FIFO36 Component Simulated in FAST Mode in the ISE 10.1 Release Compared to Legacy Model in the ISE 9.2i Release |
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Simulator and version
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Average percentage simulation run time improvement
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Average speed up factor on simulation run times
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ModelSim 6.3c
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14%
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1.14X
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NCSIM 6.1
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14%
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1.14X
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VCS 2006.06-SP1
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25%
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1.25X
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Conclusion
The recent adoption of the SecureIP encryption standard in the Verilog LRM and support for it by the simulation tool vendors provides a new way to deliver IP models that provide significant advantages over SmartModels. Customers using SecureIP models provided by Xilinx will have an easy-to-use seamless design flow providing significant simulation runtime improvements. This allows FPGA designers to use hard IP models in their RTL designs that provide the fastest possible simulation performance and that can run on any platform supported by the ISE 10.1 release and the simulation tool partner. The introduction of models that can be run in a FAST simulation performance mode also provides customers with an additional option to improve simulation runtime performance on some of the complex Virtex-5 FPGA programmable device primitives in the ISE 10.1 release. Xilinx will continue to work with the simulation tool partners to improve simulation performance with these and other primitives in future releases.
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