FPGAs have always benefited from the rising waterline of Moore’s Law. When the first programmable devices hit the market, the price of programmability was very high. The amount of density, power, and performance you gave up to gain the privilege of programming your hardware on your desktop or in your system was so large that only a few specialized applications could justify the programmability penalty. As process nodes passed, however, Moore’s Law worked in our favor. As transistors got cheaper, faster, and thriftier on power, the relative disadvantage of FPGAs disappeared for more applications, and the market broadened.
Actel has surfed a similar wave when it comes to non-volatile flash-based FPGAs compared with traditional SRAM-type devices. Flash-based FPGAs have always offered certain attractive advantages – very low static power, single-chip operation, live-at-power-up simplicity, high radiation tolerance, and good design security. However, the penalty box included some often show-stopping biggies like lower density (and thus higher cost) and lower performance. In recent times, however, flash-based FPGAs have gained enough relative ground that they can meet the density, feature, and performance targets of many more applications – thus their advantages come into play and differentiate them.
The company has cleverly kept their messaging centered on the most significant of those differentiators, putting all their energy into energy. Very low static power is a compelling advantage for many applications, particularly those where you’re running on batteries. While focusing so much marketing effort in reminding us that “Power Matters” (probably something we already knew), Actel is really pointing out that their flash-based devices maintain a significant margin of victory on the coulomb-counting front.
If Actel’s efforts were nothing more than marketing, we wouldn’t be all that interested. However, they continue to attack low-power programmability on the engineering front, and that’s something we should talk about. This week, Actel announced another new line of super-low-power FPGAs, dubbed IGLOO PLUS. The thing that’s getting “PLUSSED” in this case is I/O. The new family has a big bump in the relative user pin count compared with the standard IGLOO family – Actel says 64% more. Each device has four banks of I/Os, whereas the 125K and smaller devices in the regular IGLOO family have two banks each. I/O features include hot swapping, Schmitt trigger inputs, and the company’s now ubiquitous Flash*Freeze single-pin bus hold scheme.
Actel’s low-power lineup now includes four families – ProASIC3, ProASIC3L, IGLOO, and now IGLOO PLUS. Each family offers a different mix and tradeoff point between the design-critical variables of speed, power, density, and I/O capability. ProASIC3 offers the highest density and performance with a modest power penalty. IGLOO offers the absolute best power efficiency at the cost of speed, density, and I/O. ProASIC3L compromises by giving a mid-point of the power/speed tradeoff between ProASIC3 and IGLOO. Now, IGLOO PLUS gives IGLOO-like power consumption with a higher ratio of I/O to core fabric.
The higher I/O ratios let Actel maximize another metric that’s important to many mobile and portable device design teams – functionality per mm2. Actel claims that the new family gives more logic and I/O for a given package footprint than any competitor, and does so at a lower static power point. In an 8X8 package, the new family can give you 68K “system gates” (Don’t ask, you don’t want to know.) and 157 I/Os with a static power draw of only 10µW. If you’re designing a portable device and want some programmable logic on the board to save your job once marketing figures out what they forgot to tell you, a couple of BOM bucks, 64mm2, and 10µW is a small price to pay for the ability to sleep at night. You can integrate a lot of stuff from your board into one of these little devices too, so more often than not they pay for themselves on every count.
IGLOO is available in a range of package sizes and pitches from the 4×4 UC81 with 66 I/Os up through a 10×10 CS281 with 215 I/Os. If you already have a high-density board, you can get a really small footprint with the smaller pitch packages. If you’re trying to stay lower-cost and lower-tech on your board design, you can give up a little package size for roomier pin spacing.
In the spirit of investing engineering to match their marketing, Actel has also built a nice suite of power-enabled design tools to go with their offering. Actel’s Libero Integrated Design Environment (IDE) includes both power analysis and power optimization features. The analysis environment allows you to create profiles based on the functional modes and duty-cycles of your design. This gives you a more real-world accurate estimate than simple vector/toggle-based tools. The tools boil down the whole equation to give you a battery life estimation as well – and a simple accounting feature can save you a lot of time on the calculator, as well as preventing a few of those sneaky and embarrassing errors that come back to haunt you at the end of the design cycle “Ah, I entered an extra zero – that’s why the batteries only lasted three minutes. Dang.”
On the optimization side, Libero now includes power-driven layout that brings in a power-optimization phase after the “normal” timing/area optimization tradeoffs are made. This way, you can meet timing and area budgets first, and then get the lowest power possible for a version of your design that will actually meet spec, rather than doing power optimization and then finding out that you now can’t meet timing.
By broadening their power portfolio, Actel is showing that they’re serious about this power business. The company that once sold some of the most expensive FPGAs ever built is now battling it out with the big SRAM-based FPGA companies for single-digit sockets in high-volume, power-sensitive applications. The wider range of device family options lets Actel capitalize on the advantages of their flash technology while answering the wide range of customer needs from performance to density and features, and now to relative pin count. These days in the FPGA market – where power is low, the stakes high.
