Custom IC design has always been the extreme sport of electronic engineering. The design teams that could successfully put together a complex ASIC system-on-chip (SoC) design on the smallest available process geometry tend to be made up of the best and the brightest – the elite talent of the engineering crowd. IC designers have always blazed new trails, making the rules rather than following them, and constantly cutting their technological teeth on the sharpest edge of advancing technology.
During the forty-plus years that we’ve watched Mr. Moore’s self-perpetuating prognostication run its unbelievable course, an odd pattern has emerged in the population of IC-savvy engineers. In the beginning, our numbers were small – only the fantastic Fairchild few and a handful of other in-the-know visionaries carried the seeds of the nascent IC industry. Over the years, as the adoption of integrated circuits exploded, so did the number of qualified designers.
For a time, IC design got easier. The electronic design automation (EDA) industry emerged, and the tools they provided simplified and canonized the complex task of concept to mask. More companies could develop application-specific devices, so more companies did. The promise of lower power, smaller footprints, higher reliability, and lower BOM cost was far too tempting to dissuade design teams from tackling the ever-easier ASIC challenge. During the heyday of ASIC design, tens of thousands of engineers worldwide flashed business cards proclaiming them “ASIC Designers.”
Then, a strange thing happened.
As process geometries got smaller, the IC design problem became more complex, more time-consuming, and more expensive. EDA and friends could not keep pace with Mr. Moore, and the cost and risk involved in creating a verified set of masks with a verified design on them increased exponentially. For the masses, alternatives such as ASSPs, FPGAs, and structured ASICs emerged, and legions of design teams began to abandon the do-or-die stress of Design Spin Russian Roulette for more modest methods. With each passing process node, the number of ASIC design starts shrank and, with it, the number of engineers qualified in the exacting discipline of IC design and verification.
For companies that make their living on the ASIC ecosystem, this is a dangerous trend. EDA, for example, has now spent the better part of a decade creating increasingly more sophisticated tools to solve ever-more-challenging design problems for a shrinking number of end-users. This threatens the vital supply of design tool technology needed by the companies that form the foundation of almost all semiconductor advances. If design tool technology stagnates, the entire semiconductor industry stalls. If EDA companies can’t continue to engineer a means to profit from their own progress, however, that is exactly what could come to pass.
Some players at the party have slain these economic dragons with innovative business models. In the IP industry, for example, royalty-based rewards have allowed the providers to continue to profit as the number of design starts decreases while the average unit volume climbs. By participating in the profits of the end product, IP suppliers have insulated themselves from the isolation of the elite.
Over the past couple of years, however, the IC design community has been abandoned by the unlikeliest of its allies. The media and analyst community that have tracked and reported on the progress of the ASIC and EDA industry for the past several decades have begun defecting in droves. From Dataquest’s well-publicized elimination of EDA coverage to EE Times’s more recent editorial shakeout, leading companies that have been an integral part of the ASIC community have all but vanished from the scene.
For that reason, we are excited to welcome you to IC Design and Verification Journal. For the past five years, Techfocus Media has made a business of serving important, focused segments of the electronics engineering community with intelligent, insightful, and useful publications. With IC Journal, we will bring you the latest news and analysis on the trends, tools, and technology of IC design and verification – from the evolution of advanced design methodologies like ESL to the latest methods for accelerating the process of verifying billions of transistors worth of logic.
With design teams already testing the water at 45nm, a plethora of problems are peering through the portals. Leakage current, sprawling clock nets, resistance effects in routing, patterning challenges, and many other demons lurk in the deep submicron waters below today’s 65nm depth. ESL, DFM, RET, and a host of other acronyms are rushing to the rescue, however, and IC Design and Verification Journal will be there with you – giving our two cents worth on the trillion dollar industry supported by you, today’s advanced IC designers.
Each week, our editors will weigh in on a current topic with an in-depth feature article or two. We pride ourselves in writing a step away from the journalistic norm. If you find humor in everyday design work, or if you’re the kind of designer that’s fascinated both by System Verilog and by the vintage action figure collection the guy in the next cube maintains, you’ll probably never miss an issue. We’ll also bring you our own brand of fun and fascinating webcasts where we go one-on-one with the experts while kicking sand in the face of the mainstream webcast format. We’ll also bring you daily news from the front lines of ASIC, EDA, IP, and COT, and drop in periodically with extras like our topic-focused white paper spotlights.
We also invite you to drop in and kick around the more controversial topics in our reader forums at JournalForums.com, and when the time comes to upgrade your job description, you might want to browse the listings in our JournalJobs.com job board. If you’re new to Techfocus Media publications, you might also want to check out some of IC Journal’s siblings. For example, if you’re using FPGAs for prototyping or verification of complex ASIC designs, you may already be a subscriber to our industry-leading FPGA Journal, or, if you’re heavily involved in embedded system design, you’ll want to watch our fast-growing Embedded Technology Journal.
Most of all, we want to serve you – providing the information you need to get ahead in your work, and keeping you a little entertained in the process. If you have suggestions for making our publications more useful, drop us a line. We’re always happy to hear from you.
