Now that it is officially OK to use FPGAs in battery-powered devices, we’re seeing two groups of designers converging on the low-power FPGA design topic. First, there are those who have been working on low-power and portable applications for years and are just now taking on FPGAs for the first time. Second, there are those who have been doing FPGAs for years, but have never needed to perform power-conscious design because their FPGA designs were always run from small dedicated nuclear power facilities. While both of these groups are learning new techniques, the thing they have in common is the need for low-power FPGA design tools.
Actel has just released a new version of their Libero development tools (version 8.1), and the focus is all on improving low-power design. It makes good sense. Actel currently has the champion among low-power FPGAs (if you’re judging based on power consumption) with their Igloo family. Igloo isn’t just a little bit lower power than the other low-power FPGA families; it’s in a whole different category. Because Actel FPGAs are true non-volatile devices, configured with flash cells instead of the SRAM-like cells used in mainstream FPGAs, they have considerably lower power consumption. Flash doesn’t require power to hold state, so a flash-based FPGA isn’t on the meter when it’s not working. Even holding I/Os at the proper state, keeping SRAM and register contents, and turning off clocks (what Actel calls “Flash*Freeze” mode), quiescent current is in the micro-amps. An assortment of low-power modes allows you to back off the FPGA to be just as miserly as you need to be at any given time, while maintaining the level of functionality required by your system. Because of the device architecture and 1.2V supply, dynamic power is also very low.
Just having a low-power FPGA, however, doesn’t mean your design will automatically do the right thing to save power. You have to think about power consumption in every part of your system design, and you need tools to help you with the job. Actel’s newest Libero includes tools for both estimating and reducing power consumption in the FPGA portion of your system.
There are a number of techniques for saving power in FPGA-based designs. First, and simplest, is to turn off the entire FPGA when it’s not in use. Of course, this isn’t as simple as it seems. As we mentioned above, Actel’s non-volatile devices are easier than most because they don’t lose their configuration, and they require a complex, lengthy, and power-wasting re-configuration when power is re-applied. However, you still need to consider things like what state your I/Os need to maintain while the FPGA is off-line, how the FPGA will be re-awakened, and what happens with the contents of memory and registers during the sleep period. You want the sleep and wake-up process to be smooth and glitch-free.
In addition to turning off the whole FPGA, you might want to just turn off clocks or tri-state registers when signals don’t need to be driven. In some cases, the FPGA can be used to perform some system management functions such as monitoring external inputs for and re-awakening parts of the system during periods of sleep or hibernation.
Second on the list is to keep clock frequencies low. At the macro level, you want to choose the lowest frequency that will get the job done in active mode. Slower toggling always burns less power. Second, you want to be sure you’re not clocking anything that you don’t actually need. Of course, you can get fancy with this technique. Third, you want to be sure to group your clock domains so that parts of the system that don’t need fast clocks aren’t wasting power deriving their clocks from a high-speed clock domain. Finally, you can look at frequency scaling where you slow down the clock on the fly as system demands change.
Actel has added some new tricks to the bag in this version of Libero. First, they have attacked power at the place-and-route level. They have added power-driven layout that minimizes net capacitance for power-critical nets by both placement and routing optimizations. The company claims that this technique can reduce dynamic power by about 13% and sometimes by as much as 30%. The criticality of nets is determined by an analysis of the design with user-supplied vectors and models of device activities. Actel says that a typical design spends as much as 40% of total power in nets and clocks (the remainder in I/Os, leakage, and active dissipation in gates and memories), so a reduction in net- and clock-based power in layout can make a big dent in the overall power budget. The hardest part to crack in FPGA design is the I/O chunk, because that is typically a function of what the FPGA is driving, rather than anything in the FPGA design itself.
The second power-reduction technique Actel is adding to the picture is Hazard analysis and reduction. The company claims that a large percentage of total power in a design can be the result of hazards – logic elements that are toggling multiple times during a clock cycle. By analyzing hazards and providing a prioritized report, the software helps you cut down on unwanted transitions and reduce the power wasted by hazards.
Of course, it is difficult to manage, prioritize, and execute a power-reduction strategy without accurate estimates of power consumption. This is perhaps where the biggest improvements have come in the latest Actel suite. Libero 8.1 allows you to create a profile that describes your system behavior in normal operation – how much time in active mode, Flash*Freeze mode, standby mode, and sleep mode. Libero’s SmartPower analysis tools use that profile to give you a more accurate picture of where the energy is going in your design so you can identify what areas to attack. In addition to the default modes listed (which are native to the device), you can create your own modes to describe design-specific states like, perhaps, power-saving modes where you’ve reduced clock frequencies temporarily. SmartPower will then allow you to generate reports broken down by mode, by type of power, by power rail, and in terms of battery life. You can tell the system the capacity of your battery, and it will tell you how long that battery will last and give a breakdown of where the energy will go.
Sometimes, the peak power is the critical commodity. Actel’s new software can do a cycle-accurate estimation of power consumption using a set of vectors you supply and can tell you where the spikes are in your power profile. In some applications, this peak power is the critical design factor. Speaking of vectors, however, you’ll want to consider carefully the vectors you use for power estimation. Many times, your simulation vectors are created to verify the functional correctness of the design. As such, they may have a disproportionate focus on corner cases and failure modes. These functional verification vectors don’t often represent “normal” use of the device, and therefore aren’t good for power profiling. It pays to have a separate set of vectors for power analysis that look more like a typical day at the office for your FPGA rather than a run around the obstacle course.
Actel’s new Libero is available now, and it is compatible with the entire range of the company’s FPGAs. The addition of this much power functionality to the design tool suite boosts what is already the premiere FPGA platform for super-low-power design. Combined with Actel’s recent announcement of the tiniest packages in the industry, the non-volatile (single chip) nature of flash-based FPGAs, and the relatively low price point, these power-pinching features should land Igloo devices in a lot of new mobile and handheld sockets over the coming months.
