High-speed system interconnects have a large impact on integrated circuit (IC) package design. High-speed connectivity requires fabrication of packages that are able to support very fast varying, broadband signals with good signal integrity (SI). Based on Moore’s law, on-chip clock frequency doubles every 18 months and the intrinsic delay of the gate decreases exponentially to a few picoseconds (ps). Increasing I/O counts add another element to this equation. Rent’s rule states that the number of I/O will double in the next ten years, which means that there will be a lot more signal pins in a smaller area. And, in turn, the smaller dimensions of chip packages make SI problems more acute when compared to PC board. Poor signal integrity means added costs, delayed product releases, and even lost revenues. The cost of ignoring signal integrity can easily reach millions of dollars, especially given how important time-to-market is in today’s marketplace.
Signal integrity challenges of Faster and Wider I/O
As system interconnect speeds increase, transition periods decrease and signals have faster and faster switching characteristics, namely, faster rise and fall rates in hundreds of picoseconds. Since most SI problems are directly related to dV/dt or source-drain current transition (dI/dt), faster rise times negatively impact SI effects such as reflection noise, crosstalk noise and power/ground switching noise.
Reflection noise
Impedance discontinuity along the signal transmission path is the root cause of reflection noise. When a signal reaches the end of an improperly terminated transmission line, some of the energy within the signal will return along the same line. Reflections also occur when signals jump routing layers and impedance values are discontinuous at the boundary. This could be the result of manufacturing variations, design considerations, etc. When a trace is routed over planes with via holes, stubs, gaps at different locations or within the proximity of other traces, impedance discontinuity will occur and reflection can be observed. In high-speed systems, reflection noise (Figure 1: Reflection Noise) increases time delay and produces overshoot, undershoot and ringing. Reflection noise can be minimized by controlling trace characteristic impedance, eliminating stubs and by using appropriate termination.
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Figure 1: Reflection Noise |
Crosstalk noise
Crosstalk is caused by electromagnetic coupling between multiple parallel transmission lines. The transmission lines can be either PCB traces or vias between package balls and the PCB. In packages, coupling between vias is more significant than trace coupling. A quiet line (victim) when coupled to an active signal line (aggressor) can pick up noise causing false logic switching (Figure 2: Crosstalk from Aggressor to Victim). In larger packages where multiple active lines switch simultaneously, crosstalk can induce power/ground noise. When two lines switch in the same direction, either from high to low or low to high, extra delay is introduced. This delay can significantly increase or decrease the sampling window. Crosstalk can be controlled by line spacing, placement of ground pins between signal pins and keeping reference planes close to signal pins (by reducing the loop inductance which is a function of area of the return current loop).
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Figure 2: Crosstalk from Aggressor to Victim
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Power/ground noise
Power/ground planes and vias within a chip package form power distribution networks. Transient currents as large as 20A are drawn by a hundreds of signals switching simultaneously under 200 ps transition time. The dI/dt when the input to a gate is changed from low to high or vice versa multiplied by the package inductance (L) causes fluctuations, or simultaneous switching noise (SSN: Δv = L.dI/dt)) between power and ground planes. The I/O supply current always travels in a loop, and in the breakout region of large packages, multiple I/Os can share a common return loop. The location of power/ground and I/O pins determine the size of the loop (Figure 3: Package Pin-out and Inductance).Via crosstalk couples the loops formed by the I/O and the common return path exacerbating the problem.
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Figure 3: Package Pin-out and Inductance |
SSN can impact system timing, cause false logic switching, introduce noise in the power rail and create output jitter and increase radiation at resonant frequencies. Lowering core voltage to reduce SSN reduces noise margin and makes the package more susceptible to signal integrity problems. SSN can be reduced by providing proper return paths to signals. The return current will travel on a reference plane, either power or ground that is in close proximity to the signal.
Solving the Signal Integrity Challenge
Fortunately for the FPGA designer, the SI issue is addressed today by the FPGA supplier. Advanced package design techniques used in the latest generation FPGAs such as the Xilinx Virtex™-5 family help to greatly simplify PCB design. This means that digital logic and PCB designers do not have to worry about solving signal integrity issues created by packaging.
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Figure 4: Virtex-5 Sparse Chevron Packaging |
Sparse Chevron pinout pattern for minimal noise
The key to minimizing SSN is lowering the package inductance. The pinout pattern of the FPGA package determines the loop inductance. In the FPGA illustrated in Figure 4 (Figure 4: Sparse Chevron Packaging), every signal pin is adjacent to a GND/VCC (return) pin, and the ratio of signal pins to a return pin is just 4:1. The abundance of return pins, along with pin distribution for small loop area, provides for desirable low-impedance return paths. This reduces the inductance of the signal path from 15.6 nH down to 4.9 nH (Figure 5: Reducing the Mutual Inductance), helping to maintain noise performance more effectively than with traditional package designs.
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Figure 5: Reducing the Mutual Inductance |
Narrow banking structure for easy signal breakout
In the previous generations, FPGA I/O banks have typically been divided into quads or octets along the centre of the package. Two I/Os within a bank can be physically far apart and as such will have different trace components — different layers, additional vias, and so on. This causes impedance mismatches and hence reflection noise. In newer FPGAs such as those highlighted in Figure 6 (Figure 6: I/O Banking), the outer banks are only three or four pins deep, so up to eight banks can reside along the periphery of the package enabling easy breakout into the PCB. This helps trace impedance matching and improves SI.
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Figure 6: Virtex-4 vs. Virtex-5 I/O Banking |
On-Chip Decoupling Capacitors for Cleaner Power Supplies
A network of decoupling capacitors is required to filter out mid-range and high-frequency noise from a power supply. These decoupling capacitors increase PCB component count and footprint, adding to the cost burden. The latest generation FPGAs have these decoupling capacitors embedded inside the package, significantly reducing the number of external components on the PCB.
Summary
Faster and wider system interconnects are creating a new set of challenges. With ASIC implementations, the chip and package must be co-designed. By contrast, the introduction of next-generation FPGAs with advanced packaging techniques makes life easier for digital logic and PCB designers as the co-design of chip/package is handled by the FPGA vendor. Techniques such as Sparse Chevron pinout, narrow banking structures and on-chip decoupling capacitors minimize noise, ease signal breakout and ensure clean power. Clearly, designing systems using FPGAs with advanced packages solves the signal integrity challenge and in addition improves time to market, reduces risk and potentially saves millions of dollars.
About the Author
Navneet Rao is a technical marketing manager at Xilinx specializing in high speed connectivity solutions. Previously Rao led teams in architecting and designing transceivers and switch fabric ASICs at Mindspeed Technologies (Hotrail, Inc). Rao also worked in product development teams at Philips Semiconductors and LSI Logic. He is an active member in trade associations such as FSA, RapidIO, PCI Express, and HyperTransport. Rao has been an invited speaker at a number of seminars with industry experts including the RapidIO Trade Association and The Linley Group. Rao earned his degree from the Indian Institute of Technology, Kharagpur, India.
References:
[1] Signal Integrity chapter by Raymond Y. Chen of Sigrity, Inc.
[2] How FPGA packaging drives signal integrity by Panch Chandrasekaran, Xilinx, Inc.
[3] Virtex-5 family advanced packaging, a white paper by Panch Chandrasekaran, Xilinx, Inc.
