From about the time of the announcement of their foundry partnership with Fujitsu, Lattice Semiconductor has been doing things a little differently. Step by step, they’ve been establishing a real, credible presence in the fast-expanding FPGA market. Prior to that, their FPGA-related efforts had been less than stellar, and the company had survived on a strong heritage of CPLD offerings.
After establishing an FPGA beachhead with a competitive array of 130nm low-cost FPGA families, the company shoved their way into the elite 90nm FPGA race with a full line of well differentiated low-cost and high-end offerings. During that span, two products – the non-volatile flash/SRAM Lattice XP and the low-cost-serdes-havin’ ECP2M — have stood out as clear concept leaders, attracting significant industry attention with their mold-breaking, market-making features.
Comparative quiet was the reception of their highly-capable LatticeSC high-end 90nm FPGA family. A stand-up competitor in its own right, it needed time to build the market momentum of heavily-marketed rivals like Xilinx’s Virtex-4 and Altera’s Stratix II. SC, however, had a couple of “to be announced later” features up its sleeve – the hard IP landing-zone for what the company calls “Maco” blocks and a cost-reduction strategy announced this week called “FreedomChip”.
Now, the specific features of LatticeSC start to take on more meaning. The combination of a high-end FPGA with a production-cost-reduction scheme like FreedomChip makes FPGAs practical for a whole new range of sockets in higher-volume applications farther out toward the periphery of the triple-play onion. The high-end FPGA has always been at the core of the network, where systems like high-end switching appliances needed the latest and greatest FPGA technology, almost without regard to cost. As you move out on the network, however, closer to the client end, the volumes go up and the FPGA content goes down dramatically. Adding a cost reduction scheme moves FPGAs into higher-volume sockets that might otherwise be occupied by some form of ASIC.
The FPGA-based prototyping flow is well established today. Even high-volume, high-density ASIC projects often begin with an FPGA-based prototype. There are also a number of vendors like AMI that offer direct or semi-direct conversion of working FPGA design/prototypes into ASICs. Now, with the introduction of FreedomChip, all of the vendors with high-end FPGAs offer their own proprietary cost-reduction path.
FreedomChip offers cost reduction in the 30-75% range, depending on the density of the original FPGA design. The process is quite simple, beginning with your developing and testing your FPGA design as usual. If you know in advance that you’re planning to use FreedomChip as a cost-reduction strategy, there are a few things you can keep in mind to make your later work easier. First, you can start out using Lattice’s ISPLever tools in “FreedomChip” mode. Since scan-based methodology will be used to test your volume production devices, you’ll want to follow the usual ASIC rules for scan-based testability, including limiting or eliminating asynchronous logic loops. Since the core logic will not be reprogrammable, you also can’t rely on in-system reprogrammability for your FreedomChip design. Certain parameters like SerDes pre-emphasis and equalization, I/O electrical characteristics, PLLs, and several others can still be changed in the field, but the core logic captured in the LUT fabric must be the same as what was tested for each device. Finally, you’ll want to avoid local set/reset in favor of global ones to preserve the local flip-flop resources that are used to insert the scan logic during test insertion phase.
Once your design is working the way you want in an FPGA, you will plunk down the first installment of your $75K NRE and send your FPGA netlist to Lattice. Lattice will use a combination of Synopsys Tetramax and their own technology to generate a scan test program for your devices, achieving 99% or more coverage. Lattice will forward sample devices to you for on-board testing along with a test coverage report showing the kind of test coverage you should expect. Within the tools, you’ll also be able to see where issues like asynchronous loops may have impacted your test coverage.
Behind the scenes in the design tools, Lattice takes advantage of a special 2-input register that accompanies each LUT on the LatticeSC device. In FreedomChip mode, this register enables insertion of the scan logic, making the test insertion essentially resource-free. The power consumption of your design should be equivalent to the FPGA version, and there is only a very nominal (5% or less) performance impact from the scan overhead.
Once you’re happy with the test coverage and sample parts, you sign off, and, just like Book-of-the-Month Club, your cost-reduced devices will begin to arrive in the mail. OK, maybe not just like that, but the volume parts will be delivered 8-12 weeks after your final netlist goes in.
Lattice’s FreedomChip falls somewhere between the solutions offered by Xilinx and Altera in its approach. Like Xilinx’s EasyPath, FreedomChip is not a re-spin of your design into a mask-programmed ASIC. A FreedomChip device is still the exact same die design as your original FPGA. The difference is in the type of testing that FreedomChip devices must pass versus those of devices that will be sold as general-purpose reprogrammable FPGAs.
All of the dies must first go through “signature analysis” to vet out those with systemic failures. The dies that remain will become either regular production FPGAs or FreedomChip devices. Those that pass the complete set of FPGA tests get binned as FPGAs. The FreedomChip devices go through the design-specific tests to verify that your design will work correctly. These tests consist of a design-specific block test to verify the hard-IP blocks used in your design and the scan-based vector testing using the Tetramax vectors generated for your netlist.
Compared with using a production FPGA, your unit costs are much lower, but you give up most of the reprogrammability offered by an FPGA. Compared with a structured ASIC solution (such as Altera’s HardCopy), you get a faster turnaround time, typically lower NRE, and less board-level re-engineering. You don’t, however, get HardCopy’s power reduction and potential performance increase.
“The main thing that differentiates FreedomChip is our ASIC-strength scan-based testing methodology,” says Shakeel Peera, director of strategic marketing for high-end products at Lattice Semiconductor. “We can achieve much higher test coverage, over 99%, which is significantly better than other approaches used in the industry.”
FreedomChip will be enabled by the upcoming 6.1 service pack 2 release of Lattice’s ISPLever tools scheduled for release in a few weeks. The FreedomChip features are enabled by a special license, and customers must be pre-qualified. (Don’t go trying to bypass the gatekeeper by mailing in your netlist and 75,000 unmarked $1 bills in brown paper bag.)
Lattice’s new FreedomChip devices should be popular in the storage industry in mid-to-high-range servers where high volumes make normal high-end FPGAs a questionable choice, but where high-speed serial I/O is becoming a necessity. They also should find many socket homes in wireless access base stations where both cost and performance are becoming critical and volumes tend to run in the thousands to tens-of-thousands of units.
