With the usual next-node battle cry of “power, performance, price, and productivity,” Altera sailed into sixty-five-nanometer territory today with the announcement of their much-anticipated Stratix III 65nm high-performance FPGA family. 

Altera has put considerable focus on power with this family, bringing in power-targeted architectural changes paired with powerful design tool support.  For years, power in FPGAs was not an important consideration.  The people paying the big bucks for older-generation FPGAs had power to burn along with their cash.  As times and technologies have changed, however, so has the power picture.  Millions of transistors have turned into billions, megahertz have multiplied, and leakage currents have leapt into prominence, as feature sizes (and thus gate oxides) have continued to shrink.

On the system side, FPGA power has gained prominence, too.  As bandwidth requirements have risen, form factors have shrunk, and heat has become an issue.  Also, with FPGAs moving from supporting cast to starring roles in many systems, they have taken the spotlight in power consumption as well.  The result of all this is that Altera saw a chance to make power a clear differentiator with Stratix III, and they’ve made significant strides with their efforts.

With 65nm, we expected supply voltages to be down to 1.0V.  Altera has thrown us a bit of a surprise with both 1.1V operation for maximum performance and 0.9V for minimum power consumption. The lower voltages help with the dynamic power picture right from the start, and the 0.9V option offers to cut static power by over half from Altera’s 90nm Stratix II numbers. 

Altera has created new logic cells that can each operate in one of three power modes.  Low-power mode offers about a 70% power reduction from logic cells in previous-generation devices.  For non-performance-critical sections of your design, Altera’s tools will automatically select low-power mode where it is appropriate.  There is also a “medium” mode that offers more performance with a power savings of about 50% from previous-generation cells, and a “high-performance” mode that still manages to use 30% less power than their 90nm Stratix II. 

Intelligence in the design software picks the appropriate performance level to give you maximum power savings while still meeting your design’s timing constraints.  This means, of course, that you’ll want to avoid the old trick of over-constraining your timing in order to get the “best performance” out of your design.  That over-constraining will now cost you power, as you won’t be taking advantage of the maximum power savings available from this flexible architecture.  Used properly, however, Altera expects that you will save around 50% in total power compared with the same design running on Stratix II.

While hitting the power problem hard, Altera has not failed to deliver on the other “Ps” of a Moore’s Law move to a new node.   The company claims that performance is up 25% from previous generations, and density has doubled, lowering the effective price per “gate” once again.  We have reached the point in process shrinks where everything no longer comes along for free.  In the old days, everything almost automatically improved with each process step.  Power, performance, and density all scaled with the geometry.  Now, however, thanks to a number of factors, design teams are forced to choose one or two of the benefits at the expense of the others.  It appears that Altera took Mr. Moore up on the additional density, kept performance increase to a manageable level, and took the power issue into their own hands with the architectural and tool improvements described above.

In terms of features, Altera has loaded on the memory and DSP blocks with this generation.  In a nod to their archrival, Altera says that they will be offering three new “variants” with Stratix III – one balanced for general purpose applications, one with more memory and DSP resources for compute-intensive DSP acceleration use, and one for high-speed interconnect applications that will feature integrated SerDes transceivers.  Altera also says they plan to continue their HardCopy structured ASIC migration path from Stratix III.  HardCopy gives Altera a leg up on cost reduction (as well as performance improvement and power reduction) for higher-volume applications, and brings the Stratix architecture into many markets where FPGAs would otherwise not be an option.

The rest of the features of Stratix III are in line with what we would expect from a continuation of the Stratix II strategy.  Previously announced capabilities and architectural features such as the ALM logic modules, Tri-Matrix memory and design security capabilities continue in Stratix III.   Stratix III will also be compatible with Altera’s full line of IP, including their popular Nios II soft-core processor for embedded applications using FPGAs as a system-on-chip platform.

Missing from the above table are the specifications for the third variant – the one with high-speed serial transceivers.  This family, Stratix III GX, will be announced at a later date, as will the HardCopy structured ASIC conversion for Stratix III.

Down in the details, Altera has stuck with their PLL clocking strategy, offering a wealth of resources broken down into global, regional, and periphery networks organized in a hierarchical structure.  It appears that FPGA companies in general have learned hard lessons from the days when lack of clocking resources was a major design constraint, as modern FPGAs seem to offer an abundance of clocking capabilities.

On the I/O front, Altera has built a strategy where devices are vertically interchangeable in the same package.  If you’re designing to a particular pinout and need to swap to a different die size, you can keep the same package that you’re already designing onto your board.

Altera says that design tools for Stratix III are available today, engineering samples will be available in Q3 2007, and production quantities are expected later in 2007.   Their reference on pricing is an EP3SL150 at 1000 units in 2007 at $549 USD.  Altera also says that Stratix III support will be available from third-party tool suppliers like Aldec, Magma, Mentor, and Synplicity.

Now that the two largest FPGA vendors have announced 65nm product families, how do things stack up?  From an architectural perspective, there is perhaps more alignment than at 90nm.  In the previous generation, with Altera’s Stratix II matched up against Xilinx’s Virtex-4, Altera had already broken the LUT4 barrier with their ALM architecture, and Xilinx had begun to branch into multiple-variant mode with their LX, SX, and FX versions.  Now, at 65nm, Xilinx has followed Altera’s lead on the LUT6 architecture, while Altera is moving toward Xilinx’s plethora of product variants with different mixes of features.  When it comes to your application, however, the details will tell the tale, and you should pick the device that best fits your specific needs.  Just don’t forget to consider the impact of factors like design tool familiarity in your equation.

Stratix III certainly has the trappings of a worthy successor to Altera’s successful Stratix and Stratix II lines.  Given Altera’s execution against their stated power, performance, and price goals, it looks like the 65nm technology will continue to spur growth in FPGA technology by bringing programmable logic capabilities into new markets and into new roles in existing ones.