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While trying to juggle last week’s Fall Processor Forum, the EDA Tech Forum, WiMax world, this week’s Convergence, and the upcoming SoC Conference and GSPx (just to name a few), we still managed to notice a few interesting announcements singing through the shout chorus. To start things off, we sat down with MIPS technologies to discuss a couple of their most recent directions. MIPS is a leading producer of processor IP for system-on-chip designs. Between MIPS and ARM, most of the world’s working embedded processor cores can be accounted for. The two companies have very different strategies, however, and they also tend to target different types of designs.
MIPS is unveiling what it calls “SOC-it,” which is a platform strategy aimed at filling out the ecosystem for embedded design with its entire range of processor cores. MIPS is following a strategy of collaboration in delivering and verifying the daunting array of permutations of processors, peripherals, busses, operating systems, middleware, IP standards, and software development tools. MIPS’s plan is to partner with key vendors of software tools, RTOS, hardware IP, and ESL (Electronic System Level Design) tools to produce platforms with defined sets of components and tools that are pre-verified to work together and that utilize a hardware abstraction layer (HAL) in order to protect software compatibility from changes in the underlying architecture.
The platform consists of two elements. The first, a hardware kernel available directly from MIPS, includes memory sub-systems, interrupts, and on-chip interconnect. The second includes most of the common peripherals like real time clock, serial ports, and general purpose I/O. These components can come from a variety of sources, but they will retain software compatibility by use of the HAL. MIPS is rolling out these components over the coming months with an L2 cache controller available now and a system controller slated for Q1’07.
If your system is aiming at an FPGA for an integration platform, your standards are still pretty non-standard. Both Xilinx and Lattice Semiconductor announced new, proprietary processor progress recently, and the industry as a whole seems intent on sidestepping the standard processor cores used in other embedded system platforms.
Xilinx announced a new version of their MicroBlaze soft-core 32-bit RISC processor that incorporates additional pipeline stages to improve overall performance when used with their new Virtex-5 65nm FPGAs. Their new MicroBlaze v5.00 core has a higher maximum clock frequency than its predecessors and can execute many instructions in fewer cycles, picking up some additional performance. The new core seeks to strike a better balance with the revised architecture of Xilinx’s new devices, while the older, v4.00 core is still recommended for use in their low-cost Spartan series devices.
As we covered previously, Lattice Semiconductor is playing catch-up in the FPGA-based processor race, having adopted a strategy of making their core both free and open source. Lattice’s approach may woo those who want to use FPGAs to integrate their system, don’t want to be locked into a particular vendor or technology, and aren’t interested in royalty-based models for processor IP.
Going against the grain in FPGA-based embedded processing, however, is Actel. Actel has partnered with ARM to make industy-standard ARM processors available in their ProASIC and Fusion (mixed signal FPGA) programmable logic devices. Recently, they have announced an upgrade to the ARM Cortex-M3 – offering an alternative to their already established ARM7 arrangement. Further, they have also just announced a pre-cooked, ready-to-eat MicroTCA solution that showcases the extraordinary versatility of their unique mixed-signal Fusion technology. Actel’s new MicroTCA reference platform includes reference designs with hardware, software, and IP to get MicroTCA implementations up and running fast. Their reference designs include a power module, an advanced mezzanine card, a cooling module, a carrier hub, and a power supply.
Actel feels that the potential system-management capabilities of the Fusion device combined with programmability will distinguish it from standard solutions in use today. Because the Fusion device is unique in the market, Actel is jumpstarting its adoption by applying significant resources into reference designs and platforms (such as this MicroTCA announcement) that show off the capability of their combination of a programmable-logic embedded platform with built-in analog capability.
Moving to the events side of things, the fall processor forum has mirrored the technology it is chartered to chart. While reportedly smaller than previous years, the content was focused squarely on the most daunting problems preventing processors from breaking the barriers that limit performance today – power and programming models. There is widespread agreement that the monolithic von Neumann machine has almost reached its potential in delivering workable MIPS per megawatt. The big unanswered questions revolve around how to proceed from here. With killer apps like HDTV encode crushing existing software architectures, a variety of innovative hardware configurations are stepping forward to test their mettle. From conservative dual-core compromises to wild, massively parallel architectures with non-conventional programming models, the range of opinions on bringing the industry the processing power it requires are diverse, to say the least.
As the leaves continue to fall, so will the product announcements. In the coming weeks, we’ll be focusing on a few of the most interesting trends in embedded design, as well as bringing you a few theme-based threads focused on issues common to the entire embedded community. Also, if you’re just coming back from one of the many symposia currently underway, drop us a line and share your experience. You just might get published.
