In the good old days, there was just one kind of FPGA – the “big” kind. Big is in quotes, of course, because even today’s most modest, miserly devices are bigger and faster than the best we could muster a decade ago. However, as the high end of FPGA technology rode the rocket of Moore’s Law toward the sky, becoming a viable solution for more and more complex applications, a new creature was born – the low-cost FPGA.
The concept seemed simple enough – “normal” high-end FPGAs were optimized for performance. Nothing was held back in getting the absolute best performance possible out of the flagships of the FPGA armada. Hard IP, the latest process technology, and copious quantities of die area were poured into never-mind-the-price programmable devices with the goal of getting the most LUTs we could manage flopping around at the fastest feasible Fmax.
Low-cost devices, however, were optimized for price instead of performance. Die area and manufacturing costs were king, and anything that could be spared was expunged from these (well-labeled by Xilinx) spartan devices. Prices plummeted, and low-cost FPGAs with respectable densities can now be had for the price of a good cup of coffee.
The problem with sustaining this dynamic duality, however, is competition. With no less than five programmable logic suppliers aggressively pursuing segments of the low-cost market, there is an almost irresistible temptation toward one-upsmanship. If your competitor offers one megabyte of block RAM, why not offer two? If your competitor’s device doesn’t include any hard-wired multipliers, why not add a few to yours? While you’re at it, why not stay a couple steps ahead on the I/O capabilities of your low-cost line, just so you have an advantage? The easy answer to each of those, of course, is cost. Every incremental bell or whistle that you slip into your low-end devices raises your costs a little and hurts your competitiveness with the low-low-end of the market, particularly with those customers that don’t plan to ring that extra bell.
The more subtle factor, however, is the potential for cannibalizing the sales of your high-end FPGA family. If you don’t maintain good differentiation in features, it’s hard to justify the extra cost (and margin) in the high-end device families. The predictable result of this conundrum is the dropping of high-end FPGA prices and margins and feature creep in the low-cost devices. Perhaps in the not-too-distant future, the two types will once again converge.
Lattice Semiconductor’s 90nm mega-announcement this month, including simultaneous rollout of high-end and low-cost devices, along with early warning on a cost reduction strategy and improved design tools, could make interesting waves in the low-cost market as well. Lattice’s new LatticeECP2 (EConomy Plus 2 – or you could take our multi-lingual spin on the old Lattice internal name with “El-Cheapo-Part-Deux”) has a number of features that challenge the too-early-to-be-called-traditional definitions of low-cost FPGAs. While Lattice surfs the 90nm process wave just like their more established competitors, they’ve chosen to add considerable interest to the mix by throwing in some features that could pull customers into their low-cost line from their competitors’ high-end offerings.
Several of the new ECP2 features seem particularly well placed for the target market, too. With DDR2 memory at the market sweet spot, makers of high-volume products would like to leverage the price/density performance of that product. Lattice has chosen to pre-engineer 400Mbps DDR2 support, conserving FPGA resources for other parts of your design and reducing design time and complexity in the process. They’ve also engineered support for easier field-update of device configuration so that systems can be designed with field upgradeability planned right in, along with bitstream encryption that brings security features into the low-cost domain.
Possibly most significant is their decision to include full-featured DSP blocks in ECP2, while bypassing them in their new high-end LatticeSC family. Their reasoning is that high-end FPGAs are most often used for high-speed connectivity in expensive, backplane-based equipment, and DSP acceleration is more often required in applications such as wireless, video, and imaging that also tend toward higher production volume and therefore favor a lower-cost device. If Lattice is right, their ECP2 might have a notable advantage in these high-growth application areas.
Looking at how the datasheet numbers for DSP stack up against the competition, ECP2 boasts up to 88 DSP blocks based on 18X18 multipliers that also implement accumulate, summation, and pipelining functions. Altera’s Cyclone II (By the way, don’t confuse Altera’s “EP2C” designation for Cyclone II with Lattice’s “ECP2.” This will almost certainly be a trick question on our next FPGA Journal pop-quiz.) boasts up to 150 embedded 18X18 multipliers, and Xilinx’s Spartan-3 series comes with up to 104 18X18 multipliers, but each of these comes without the additional DSP features built into ECP2’s DSP blocks.
Racking up the rest of the critical comparative stats, fabric density for Lattice’s ECP2 ranges from 6K to 70K LUTs, Altera’s Cyclone II from about 4K to 70K LUTs, and Xilinx’s Spartan-3 from about 2K to 75K LUTs. At least until we start getting “effective LUT” numbers again from vendors, there’s no apparent significant density range difference among the three. Lattice is also pre-announcing an ECP2M family, however, that extends their density range up to 100K LUTs. That density would be a sizeable foray into forbidden territory for low-cost devices and could threaten some high-end families.
In the I/O category – ECP2 ranges from 95 to 628 user I/O pins, while Cyclone II hooks us up with from 85 to 622, and Spartan-3 with 63 to 784. On embedded memory – ECP2 offers from 55Kb to 1Mb of embedded block RAM, coming in a with a little more than Xilinx’s Spartan-3E, about like Altera’s Cyclone II, and falling short of the almost 2Mb of Xilinx’s Spartan-3. The “not yet announced” ECP2M will apparently sport over 5 million bits of RAM, however, which should challenge the low-cost model to stretch once again.
One differentiator not to be overlooked is clock management. Instead of following just one of their competitors down either the DLL or PLL road, Lattice opted to go with the “all of the above” option – packing ECP2 with two DLLs and from two to six PLLs for timing control. By comparison, Altera’s Cyclone II includes two or four PLLs, Xilinx’s Spartan-3 comes with 2 to 4 DLL-based digital clock managers (DCMs), and, in one of the only places Spartan-3E outweighs Spartan-3, 3E comes with from 2 to 8 DCMs. This puts Lattice about even with the front of the pack on clocking control.
Of course, the biggest factor contributing to sales in the low-cost market is the cost. Unfortunately, that’s by far the hardest spec to check because it always “depends.” (CLICK HERE FOR OUR TAKE ON DECIPHERING THE COST OF LOW-COST FPGAs.) In the case of LatticeECP2, they’re projecting pricing at a buck per 2K LUTs “in high-volume”. That formula would peg the low-end of the line at about three bucks – right around the minimums claimed by any vendor for any part. In fact, at those prices the support and configuration logic can cost almost as much as the device itself, so it pays to evaluate super-low cost FPGAs from a total system cost perspective rather than raw part price.
On the more middling densities, the ECP2-50 device will be priced “as low as $23.95 in 100,000 unit quantities for delivery in 2007.” Since the ECP2-50 has 48K LUTs, that pretty well pegs Lattice’s $0.50 per 1K LUT point, as advertised. If anybody can figure out another vendor’s pricing, drop us a line. It appears that Xilinx’s Spartan-3E (widely advertised as two bucks in volume) for their 2K LUT version would have within 2X of the cost per LUT of the new Lattice family. The best reference for Altera’s Cyclone II pricing may be in the ten dollar per million gates range, but in the world of FPGAs, gates are a dubious concept at best (AS WE POINTED OUT HERE). If a million gates is the roughly 20K LUT Cyclone II EP2C20, then ten bucks for that part would roughly match the Lattice pricing.
Are you confused yet about competitive pricing? If you’re like us, you’ll probably stay that way. Next to airline seats, semiconductors are some of the most confusingly-priced products on the planet. The ONLY way to make a reasonable judgment is to compare total system cost based on real quotes from actual distributors. Be sure you know about actual delivery dates and volumes, too, just to avoid later headaches – but that’s the topic of a future article.
With LatticeECP2 and its soon-to-be-described sibling, ECP2M, Lattice is brewing a convincing 90nm encore to their strong entry into the low-cost FPGA market last year. While the spotlights have always been on the top side of the FPGA market, the money may end up being more at the low end over the coming decade. Lattice seems resolved to be an important player in that contest, and it will be a fun battle to watch.
